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* Remove binutils-2.24.Elliott Hughes2015-07-076998-1976710/+0
| | | | Change-Id: I26a47a29e4d16e75e21e9295504079a815c334c6
* MIPS: Update the encoding of the d16mule MXU instruction.Andrew Bennett2015-04-222-17/+17
| | | | Change-Id: I7ea5748faea472beb79e34aee8d19c4e0f37981e
* Fix as to ignore --save-tempsAndrew Hsieh2015-03-301-0/+7
| | | | | | | | | | | mips/gcc4.6 is now built with binutils-2.24 to be consistant with gcc4.8 and gcc4.9 on nan handling. Unfortunately gcc4.6 pass on -save-temps to not recognized by "as". gcc4.6 is normally built with binutils-2.21 which has fix for as to accept but ignore -save-temps. This CL catptures the same fix in binutils-2.21 Change-Id: I58095a67810f2bcf6e7594383002247a9491a901
* Add missing mtc1, mthc1, mfhc1 instructions to Ingenic's MXU patch.Andrew Bennett2014-08-292-0/+12
| | | | Change-Id: Ib83ffec3512b8306458d6ea608f730d08f5b1c10
* Add support for Ingenic's MXU.Andrew Bennett2014-08-296-4/+943
| | | | Change-Id: Ibc79d4e05b92b9f23a0b1a381d94c588f56a0749
* Update Binutils 2.24 to include mips32r6, mips64r6 and MSA changes.Steve Ellcey2014-07-03223-762/+12360
| | | | Change-Id: I24f28bc29dff188ba059388d8d5478f51da56a12
* [2.24] Silence ARM as error "MOV Rd, Rs" two low regs with clang/armv5/thumb1Andrew Hsieh2014-04-141-0/+7
| | | | | | See 92337cf27b1497415e3f345ea9292e96ced2a8fa Change-Id: Id8c37627f3a2e6ec904ac95139c144bd834e6e50
* Initial checkin of binutils 2.24.Ben Cheng2014-03-266836-0/+1964147
Change-Id: I0dfcbae6608dded6c3586bf5f4ac27e9612e70a2
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