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author | Yiran Wang <yiran@google.com> | 2015-06-23 15:33:17 -0700 |
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committer | Yiran Wang <yiran@google.com> | 2015-06-29 10:56:28 -0700 |
commit | 1d9fec7937f45dde5e04cac966a2d9a12f2fc15a (patch) | |
tree | 3fbcd18a379a05fd6d43491a107e1f36bc61b185 /gcc-4.9/gcc/config/i386/mmx.md | |
parent | f378ebf14df0952eae870c9865bab8326aa8f137 (diff) | |
download | toolchain_gcc-1d9fec7937f45dde5e04cac966a2d9a12f2fc15a.zip toolchain_gcc-1d9fec7937f45dde5e04cac966a2d9a12f2fc15a.tar.gz toolchain_gcc-1d9fec7937f45dde5e04cac966a2d9a12f2fc15a.tar.bz2 |
Synchronize with google/gcc-4_9 to r224707 (from r214835)
Change-Id: I3d6f06fc613c8f8b6a82143dc44b7338483aac5d
Diffstat (limited to 'gcc-4.9/gcc/config/i386/mmx.md')
-rw-r--r-- | gcc-4.9/gcc/config/i386/mmx.md | 36 |
1 files changed, 19 insertions, 17 deletions
diff --git a/gcc-4.9/gcc/config/i386/mmx.md b/gcc-4.9/gcc/config/i386/mmx.md index 214acde..a7d2a7e 100644 --- a/gcc-4.9/gcc/config/i386/mmx.md +++ b/gcc-4.9/gcc/config/i386/mmx.md @@ -600,20 +600,25 @@ ;; Avoid combining registers from different units in a single alternative, ;; see comment above inline_secondary_memory_needed function in i386.c (define_insn "*vec_extractv2sf_1" - [(set (match_operand:SF 0 "nonimmediate_operand" "=y,x,y,x,f,r") + [(set (match_operand:SF 0 "nonimmediate_operand" "=y,x,x,y,x,f,r") (vec_select:SF - (match_operand:V2SF 1 "nonimmediate_operand" " 0,0,o,o,o,o") + (match_operand:V2SF 1 "nonimmediate_operand" " 0,x,x,o,o,o,o") (parallel [(const_int 1)])))] "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))" "@ punpckhdq\t%0, %0 - unpckhps\t%0, %0 + %vmovshdup\t{%1, %0|%0, %1} + shufps\t{$0xe5, %1, %0|%0, %1, 0xe5} # # # #" - [(set_attr "type" "mmxcvt,sselog1,mmxmov,ssemov,fmov,imov") - (set_attr "mode" "DI,V4SF,SF,SF,SF,SF")]) + [(set_attr "isa" "*,sse3,noavx,*,*,*,*") + (set_attr "type" "mmxcvt,sse,sseshuf1,mmxmov,ssemov,fmov,imov") + (set_attr "length_immediate" "*,*,1,*,*,*,*") + (set_attr "prefix_rep" "*,1,*,*,*,*,*") + (set_attr "prefix" "orig,maybe_vex,orig,orig,orig,orig,orig") + (set_attr "mode" "DI,V4SF,V4SF,SF,SF,SF,SF")]) (define_split [(set (match_operand:SF 0 "register_operand") @@ -1288,26 +1293,23 @@ ;; Avoid combining registers from different units in a single alternative, ;; see comment above inline_secondary_memory_needed function in i386.c (define_insn "*vec_extractv2si_1" - [(set (match_operand:SI 0 "nonimmediate_operand" "=y,x,x,x,y,x,r") + [(set (match_operand:SI 0 "nonimmediate_operand" "=y,x,x,y,x,r") (vec_select:SI - (match_operand:V2SI 1 "nonimmediate_operand" " 0,0,x,0,o,o,o") + (match_operand:V2SI 1 "nonimmediate_operand" " 0,x,x,o,o,o") (parallel [(const_int 1)])))] "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))" "@ punpckhdq\t%0, %0 - punpckhdq\t%0, %0 - pshufd\t{$85, %1, %0|%0, %1, 85} - unpckhps\t%0, %0 + %vpshufd\t{$0xe5, %1, %0|%0, %1, 0xe5} + shufps\t{$0xe5, %1, %0|%0, %1, 0xe5} # # #" - [(set (attr "isa") - (if_then_else (eq_attr "alternative" "1,2") - (const_string "sse2") - (const_string "*"))) - (set_attr "type" "mmxcvt,sselog1,sselog1,sselog1,mmxmov,ssemov,imov") - (set_attr "length_immediate" "*,*,1,*,*,*,*") - (set_attr "mode" "DI,TI,TI,V4SF,SI,SI,SI")]) + [(set_attr "isa" "*,sse2,noavx,*,*,*") + (set_attr "type" "mmxcvt,sseshuf1,sseshuf1,mmxmov,ssemov,imov") + (set_attr "length_immediate" "*,1,1,*,*,*") + (set_attr "prefix" "orig,maybe_vex,orig,orig,orig,orig") + (set_attr "mode" "DI,TI,V4SF,SI,SI,SI")]) (define_split [(set (match_operand:SI 0 "register_operand") |