diff options
author | Ben Cheng <bccheng@google.com> | 2014-03-25 22:37:19 -0700 |
---|---|---|
committer | Ben Cheng <bccheng@google.com> | 2014-03-25 22:37:19 -0700 |
commit | 1bc5aee63eb72b341f506ad058502cd0361f0d10 (patch) | |
tree | c607e8252f3405424ff15bc2d00aa38dadbb2518 /gcc-4.9/gcc/config/rs6000/476.md | |
parent | 283a0bf58fcf333c58a2a92c3ebbc41fb9eb1fdb (diff) | |
download | toolchain_gcc-1bc5aee63eb72b341f506ad058502cd0361f0d10.zip toolchain_gcc-1bc5aee63eb72b341f506ad058502cd0361f0d10.tar.gz toolchain_gcc-1bc5aee63eb72b341f506ad058502cd0361f0d10.tar.bz2 |
Initial checkin of GCC 4.9.0 from trunk (r208799).
Change-Id: I48a3c08bb98542aa215912a75f03c0890e497dba
Diffstat (limited to 'gcc-4.9/gcc/config/rs6000/476.md')
-rw-r--r-- | gcc-4.9/gcc/config/rs6000/476.md | 141 |
1 files changed, 141 insertions, 0 deletions
diff --git a/gcc-4.9/gcc/config/rs6000/476.md b/gcc-4.9/gcc/config/rs6000/476.md new file mode 100644 index 0000000..3921bbd --- /dev/null +++ b/gcc-4.9/gcc/config/rs6000/476.md @@ -0,0 +1,141 @@ +;; Scheduling description for IBM PowerPC 476 processor. +;; Copyright (C) 2009-2014 Free Software Foundation, Inc. +;; Contributed by Peter Bergner (bergner@vnet.ibm.com). +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. +;; +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; <http://www.gnu.org/licenses/>. + +;; PPC476 Embedded PowerPC controller +;; 3 issue (476) / 4 issue (476fp) +;; +;; i_pipe - complex integer / compare +;; lj_pipe - load-store / simple integer arithmetic +;; b_pipe - branch pipe +;; f_pipe - floating point arithmetic + +(define_automaton "ppc476_core,ppc476_apu") + +(define_cpu_unit "ppc476_i_pipe,ppc476_lj_pipe,ppc476_b_pipe" "ppc476_core") +(define_cpu_unit "ppc476_issue_fp,ppc476_f_pipe" "ppc476_apu") +(define_cpu_unit "ppc476_issue_0,ppc476_issue_1,ppc476_issue_2" "ppc476_core") + +(define_reservation "ppc476_issue" "ppc476_issue_0|ppc476_issue_1|ppc476_issue_2") +(define_reservation "ppc476_issue2" "ppc476_issue_0+ppc476_issue_1\ + |ppc476_issue_0+ppc476_issue_2\ + |ppc476_issue_1+ppc476_issue_2") +(define_reservation "ppc476_issue3" "ppc476_issue_0+ppc476_issue_1+ppc476_issue_2") + +(define_insn_reservation "ppc476-load" 4 + (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ + load_l,store_c,sync") + (eq_attr "cpu" "ppc476")) + "ppc476_issue,\ + ppc476_lj_pipe") + +(define_insn_reservation "ppc476-store" 4 + (and (eq_attr "type" "store,store_ux,store_u") + (eq_attr "cpu" "ppc476")) + "ppc476_issue,\ + ppc476_lj_pipe") + +(define_insn_reservation "ppc476-fpload" 4 + (and (eq_attr "type" "fpload,fpload_ux,fpload_u") + (eq_attr "cpu" "ppc476")) + "ppc476_issue,\ + ppc476_lj_pipe") + +(define_insn_reservation "ppc476-fpstore" 4 + (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") + (eq_attr "cpu" "ppc476")) + "ppc476_issue,\ + ppc476_lj_pipe") + +(define_insn_reservation "ppc476-simple-integer" 1 + (and (eq_attr "type" "integer,insert_word,var_shift_rotate,exts,shift") + (eq_attr "cpu" "ppc476")) + "ppc476_issue,\ + ppc476_i_pipe|ppc476_lj_pipe") + +(define_insn_reservation "ppc476-complex-integer" 1 + (and (eq_attr "type" "cmp,cr_logical,delayed_cr,cntlz,isel,isync,sync,trap,popcnt") + (eq_attr "cpu" "ppc476")) + "ppc476_issue,\ + ppc476_i_pipe") + +(define_insn_reservation "ppc476-compare" 4 + (and (eq_attr "type" "compare,delayed_compare,fast_compare,mfcr,mfcrf,\ + mtcr,mfjmpr,mtjmpr,var_delayed_compare") + (eq_attr "cpu" "ppc476")) + "ppc476_issue,\ + ppc476_i_pipe") + +(define_insn_reservation "ppc476-imul" 4 + (and (eq_attr "type" "imul,imul_compare,imul2,imul3") + (eq_attr "cpu" "ppc476")) + "ppc476_issue,\ + ppc476_i_pipe") + +(define_insn_reservation "ppc476-idiv" 11 + (and (eq_attr "type" "idiv") + (eq_attr "cpu" "ppc476")) + "ppc476_issue,\ + ppc476_i_pipe*11") + +(define_insn_reservation "ppc476-branch" 1 + (and (eq_attr "type" "branch,jmpreg") + (eq_attr "cpu" "ppc476")) + "ppc476_issue,\ + ppc476_b_pipe") + +(define_insn_reservation "ppc476-two" 2 + (and (eq_attr "type" "two") + (eq_attr "cpu" "ppc476")) + "ppc476_issue2,\ + ppc476_i_pipe|ppc476_lj_pipe,\ + ppc476_i_pipe|ppc476_lj_pipe") + +(define_insn_reservation "ppc476-three" 3 + (and (eq_attr "type" "three") + (eq_attr "cpu" "ppc476")) + "ppc476_issue3,\ + ppc476_i_pipe|ppc476_lj_pipe,\ + ppc476_i_pipe|ppc476_lj_pipe,\ + ppc476_i_pipe|ppc476_lj_pipe") + +(define_insn_reservation "ppc476-fpcompare" 6 + (and (eq_attr "type" "fpcompare") + (eq_attr "cpu" "ppc476")) + "ppc476_issue+ppc476_issue_fp,\ + ppc476_f_pipe+ppc476_i_pipe") + +(define_insn_reservation "ppc476-fp" 6 + (and (eq_attr "type" "fp,dmul") + (eq_attr "cpu" "ppc476")) + "ppc476_issue_fp,\ + ppc476_f_pipe") + +(define_insn_reservation "ppc476-sdiv" 19 + (and (eq_attr "type" "sdiv") + (eq_attr "cpu" "ppc476")) + "ppc476_issue_fp, + ppc476_f_pipe*19") + +(define_insn_reservation "ppc476-ddiv" 33 + (and (eq_attr "type" "ddiv") + (eq_attr "cpu" "ppc476")) + "ppc476_issue_fp,\ + ppc476_f_pipe*33") + |