diff options
Diffstat (limited to 'gcc-4.6/gcc/config/i386/i386.md')
| -rw-r--r-- | gcc-4.6/gcc/config/i386/i386.md | 177 |
1 files changed, 96 insertions, 81 deletions
diff --git a/gcc-4.6/gcc/config/i386/i386.md b/gcc-4.6/gcc/config/i386/i386.md index 3bfa0b3..b1d7e5e 100644 --- a/gcc-4.6/gcc/config/i386/i386.md +++ b/gcc-4.6/gcc/config/i386/i386.md @@ -1960,7 +1960,7 @@ (define_insn "*movdi_internal_rex64" [(set (match_operand:DI 0 "nonimmediate_operand" - "=r,r ,r,m ,!m,*y,*y,?r ,m ,?*Ym,?*y,*x,*x,?r ,m,?*Yi,*x,?*x,?*Ym") + "=r,r ,r,m ,!o,*y,*y,?r ,m ,?*Ym,?*y,*x,*x,?r ,m,?*Yi,*x,?*x,?*Ym") (match_operand:DI 1 "general_operand" "Z ,rem,i,re,n ,C ,*y,*Ym,*y,r ,m ,C ,*x,*Yi,*x,r ,m ,*Ym,*x"))] "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))" @@ -2905,7 +2905,7 @@ (define_insn "*movdf_internal_rex64" [(set (match_operand:DF 0 "nonimmediate_operand" - "=f,m,f,r ,m,!r,!m,Y2*x,Y2*x,Y2*x,m ,Yi,r ") + "=f,m,f,r ,m,!r,!o,Y2*x,Y2*x,Y2*x,m ,Yi,r ") (match_operand:DF 1 "general_operand" "fm,f,G,rm,r,F ,F ,C ,Y2*x,m ,Y2*x,r ,Yi"))] "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1])) @@ -5103,7 +5103,7 @@ && reload_completed && (SSE_REG_P (operands[0]) || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(set (match_dup 0) (float:MODEF (match_dup 1)))]) (define_split @@ -5116,7 +5116,7 @@ && reload_completed && (SSE_REG_P (operands[0]) || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(set (match_dup 2) (match_dup 1)) (set (match_dup 0) (float:MODEF (match_dup 2)))]) @@ -5207,7 +5207,7 @@ && reload_completed && (SSE_REG_P (operands[0]) || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(const_int 0)] { rtx op1 = operands[1]; @@ -5248,7 +5248,7 @@ && reload_completed && (SSE_REG_P (operands[0]) || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(const_int 0)] { operands[3] = simplify_gen_subreg (<ssevecmode>mode, operands[0], @@ -5270,7 +5270,7 @@ && reload_completed && (SSE_REG_P (operands[0]) || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(const_int 0)] { rtx op1 = operands[1]; @@ -5280,11 +5280,20 @@ if (GET_CODE (op1) == SUBREG) op1 = SUBREG_REG (op1); - if (GENERAL_REG_P (op1) && TARGET_INTER_UNIT_MOVES) + if (GENERAL_REG_P (op1)) { operands[4] = simplify_gen_subreg (V4SImode, operands[0], <MODE>mode, 0); - emit_insn (gen_sse2_loadld (operands[4], - CONST0_RTX (V4SImode), operands[1])); + if (TARGET_INTER_UNIT_MOVES) + emit_insn (gen_sse2_loadld (operands[4], + CONST0_RTX (V4SImode), operands[1])); + else + { + operands[5] = ix86_force_to_memory (GET_MODE (operands[1]), + operands[1]); + emit_insn (gen_sse2_loadld (operands[4], + CONST0_RTX (V4SImode), operands[5])); + ix86_free_from_memory (GET_MODE (operands[1])); + } } /* We can ignore possible trapping value in the high part of SSE register for non-trapping math. */ @@ -5305,7 +5314,7 @@ && reload_completed && (SSE_REG_P (operands[0]) || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(const_int 0)] { operands[3] = simplify_gen_subreg (<ssevecmode>mode, operands[0], @@ -5366,7 +5375,7 @@ && reload_completed && (SSE_REG_P (operands[0]) || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(set (match_dup 0) (float:MODEF (match_dup 1)))]) (define_insn "*float<SSEMODEI24:mode><MODEF:mode>2_sse_nointerunit" @@ -5401,7 +5410,7 @@ && reload_completed && (SSE_REG_P (operands[0]) || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(set (match_dup 2) (match_dup 1)) (set (match_dup 0) (float:MODEF (match_dup 2)))]) @@ -5414,7 +5423,7 @@ && reload_completed && (SSE_REG_P (operands[0]) || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(set (match_dup 0) (float:MODEF (match_dup 1)))]) (define_insn "*float<SSEMODEI24:mode><X87MODEF:mode>2_i387_with_temp" @@ -11341,7 +11350,7 @@ (define_insn_and_split "*call_pop_1_vzeroupper" [(parallel - [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lsm")) + [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lzm")) (match_operand:SI 1 "" "")) (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) @@ -11356,7 +11365,7 @@ [(set_attr "type" "call")]) (define_insn "*call_pop_1" - [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lsm")) + [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lzm")) (match_operand:SI 1 "" "")) (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) @@ -11371,7 +11380,7 @@ (define_insn_and_split "*sibcall_pop_1_vzeroupper" [(parallel - [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "s,U")) + [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "z,U")) (match_operand:SI 1 "" "")) (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) @@ -11386,7 +11395,7 @@ [(set_attr "type" "call")]) (define_insn "*sibcall_pop_1" - [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "s,U")) + [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "z,U")) (match_operand:SI 1 "" "")) (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) @@ -11437,7 +11446,7 @@ [(set_attr "type" "call")]) (define_insn_and_split "*call_1_vzeroupper" - [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lsm")) + [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lzm")) (match_operand 1 "" "")) (unspec [(match_operand 2 "const_int_operand" "")] UNSPEC_CALL_NEEDS_VZEROUPPER)] @@ -11449,14 +11458,14 @@ [(set_attr "type" "call")]) (define_insn "*call_1" - [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lsm")) + [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lzm")) (match_operand 1 "" ""))] "!TARGET_64BIT && !SIBLING_CALL_P (insn)" { return ix86_output_call_insn (insn, operands[0], 0); } [(set_attr "type" "call")]) (define_insn_and_split "*sibcall_1_vzeroupper" - [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "s,U")) + [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "z,U")) (match_operand 1 "" "")) (unspec [(match_operand 2 "const_int_operand" "")] UNSPEC_CALL_NEEDS_VZEROUPPER)] @@ -11468,14 +11477,14 @@ [(set_attr "type" "call")]) (define_insn "*sibcall_1" - [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "s,U")) + [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "z,U")) (match_operand 1 "" ""))] "!TARGET_64BIT && SIBLING_CALL_P (insn)" { return ix86_output_call_insn (insn, operands[0], 0); } [(set_attr "type" "call")]) (define_insn_and_split "*call_1_rex64_vzeroupper" - [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm")) + [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rzm")) (match_operand 1 "" "")) (unspec [(match_operand 2 "const_int_operand" "")] UNSPEC_CALL_NEEDS_VZEROUPPER)] @@ -11488,7 +11497,7 @@ [(set_attr "type" "call")]) (define_insn "*call_1_rex64" - [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm")) + [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rzm")) (match_operand 1 "" ""))] "TARGET_64BIT && !SIBLING_CALL_P (insn) && ix86_cmodel != CM_LARGE && ix86_cmodel != CM_LARGE_PIC" @@ -11497,7 +11506,7 @@ (define_insn_and_split "*call_1_rex64_ms_sysv_vzeroupper" [(parallel - [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm")) + [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rzm")) (match_operand 1 "" "")) (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL) (clobber (reg:TI XMM6_REG)) @@ -11522,7 +11531,7 @@ [(set_attr "type" "call")]) (define_insn "*call_1_rex64_ms_sysv" - [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm")) + [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rzm")) (match_operand 1 "" "")) (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL) (clobber (reg:TI XMM6_REG)) @@ -11561,7 +11570,7 @@ [(set_attr "type" "call")]) (define_insn_and_split "*sibcall_1_rex64_vzeroupper" - [(call (mem:QI (match_operand:DI 0 "sibcall_insn_operand" "s,U")) + [(call (mem:QI (match_operand:DI 0 "sibcall_insn_operand" "z,U")) (match_operand 1 "" "")) (unspec [(match_operand 2 "const_int_operand" "")] UNSPEC_CALL_NEEDS_VZEROUPPER)] @@ -11573,7 +11582,7 @@ [(set_attr "type" "call")]) (define_insn "*sibcall_1_rex64" - [(call (mem:QI (match_operand:DI 0 "sibcall_insn_operand" "s,U")) + [(call (mem:QI (match_operand:DI 0 "sibcall_insn_operand" "z,U")) (match_operand 1 "" ""))] "TARGET_64BIT && SIBLING_CALL_P (insn)" { return ix86_output_call_insn (insn, operands[0], 0); } @@ -14616,7 +14625,7 @@ emit_insn (gen_sse4_1_round<mode>2 (operands[0], operands[1], GEN_INT (0x04))); else - ix86_expand_rint (operand0, operand1); + ix86_expand_rint (operands[0], operands[1]); } else { @@ -14640,9 +14649,9 @@ if (optimize_insn_for_size_p ()) FAIL; if (TARGET_64BIT || (<MODE>mode != DFmode)) - ix86_expand_round (operand0, operand1); + ix86_expand_round (operands[0], operands[1]); else - ix86_expand_rounddf_32 (operand0, operand1); + ix86_expand_rounddf_32 (operands[0], operands[1]); DONE; }) @@ -14787,7 +14796,7 @@ { if (optimize_insn_for_size_p ()) FAIL; - ix86_expand_lround (operand0, operand1); + ix86_expand_lround (operands[0], operands[1]); DONE; }) @@ -14862,9 +14871,9 @@ emit_insn (gen_sse4_1_round<mode>2 (operands[0], operands[1], GEN_INT (0x01))); else if (TARGET_64BIT || (<MODE>mode != DFmode)) - ix86_expand_floorceil (operand0, operand1, true); + ix86_expand_floorceil (operands[0], operands[1], true); else - ix86_expand_floorceildf_32 (operand0, operand1, true); + ix86_expand_floorceildf_32 (operands[0], operands[1], true); } else { @@ -15044,7 +15053,7 @@ { if (TARGET_64BIT && optimize_insn_for_size_p ()) FAIL; - ix86_expand_lfloorceil (operand0, operand1, true); + ix86_expand_lfloorceil (operands[0], operands[1], true); DONE; }) @@ -15119,9 +15128,9 @@ else if (optimize_insn_for_size_p ()) FAIL; else if (TARGET_64BIT || (<MODE>mode != DFmode)) - ix86_expand_floorceil (operand0, operand1, false); + ix86_expand_floorceil (operands[0], operands[1], false); else - ix86_expand_floorceildf_32 (operand0, operand1, false); + ix86_expand_floorceildf_32 (operands[0], operands[1], false); } else { @@ -15299,7 +15308,7 @@ "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH && !flag_trapping_math" { - ix86_expand_lfloorceil (operand0, operand1, false); + ix86_expand_lfloorceil (operands[0], operands[1], false); DONE; }) @@ -15374,9 +15383,9 @@ else if (optimize_insn_for_size_p ()) FAIL; else if (TARGET_64BIT || (<MODE>mode != DFmode)) - ix86_expand_trunc (operand0, operand1); + ix86_expand_trunc (operands[0], operands[1]); else - ix86_expand_truncdf_32 (operand0, operand1); + ix86_expand_truncdf_32 (operands[0], operands[1]); } else { @@ -15699,7 +15708,8 @@ (set (match_operand:DI 1 "register_operand" "=S") (plus:DI (match_dup 3) (const_int 8)))] - "TARGET_64BIT" + "TARGET_64BIT + && !(fixed_regs[SI_REG] || fixed_regs[DI_REG])" "movsq" [(set_attr "type" "str") (set_attr "memory" "both") @@ -15714,7 +15724,7 @@ (set (match_operand:P 1 "register_operand" "=S") (plus:P (match_dup 3) (const_int 4)))] - "" + "!(fixed_regs[SI_REG] || fixed_regs[DI_REG])" "movs{l|d}" [(set_attr "type" "str") (set_attr "memory" "both") @@ -15729,7 +15739,7 @@ (set (match_operand:P 1 "register_operand" "=S") (plus:P (match_dup 3) (const_int 2)))] - "" + "!(fixed_regs[SI_REG] || fixed_regs[DI_REG])" "movsw" [(set_attr "type" "str") (set_attr "memory" "both") @@ -15744,7 +15754,7 @@ (set (match_operand:P 1 "register_operand" "=S") (plus:P (match_dup 3) (const_int 1)))] - "" + "!(fixed_regs[SI_REG] || fixed_regs[DI_REG])" "movsb" [(set_attr "type" "str") (set_attr "memory" "both") @@ -15779,7 +15789,8 @@ (set (mem:BLK (match_dup 3)) (mem:BLK (match_dup 4))) (use (match_dup 5))] - "TARGET_64BIT" + "TARGET_64BIT + && !(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])" "rep{%;} movsq" [(set_attr "type" "str") (set_attr "prefix_rep" "1") @@ -15798,7 +15809,7 @@ (set (mem:BLK (match_dup 3)) (mem:BLK (match_dup 4))) (use (match_dup 5))] - "" + "!(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])" "rep{%;} movs{l|d}" [(set_attr "type" "str") (set_attr "prefix_rep" "1") @@ -15815,7 +15826,7 @@ (set (mem:BLK (match_dup 3)) (mem:BLK (match_dup 4))) (use (match_dup 5))] - "" + "!(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])" "rep{%;} movsb" [(set_attr "type" "str") (set_attr "prefix_rep" "1") @@ -15858,7 +15869,9 @@ operands[3] = gen_rtx_PLUS (Pmode, operands[0], GEN_INT (GET_MODE_SIZE (GET_MODE (operands[2])))); - if (TARGET_SINGLE_STRINGOP || optimize_insn_for_size_p ()) + /* Can't use this if the user has appropriated eax or edi. */ + if ((TARGET_SINGLE_STRINGOP || optimize_insn_for_size_p ()) + && !(fixed_regs[AX_REG] || fixed_regs[DI_REG])) { emit_insn (gen_strset_singleop (operands[0], operands[1], operands[2], operands[3])); @@ -15880,7 +15893,8 @@ (set (match_operand:DI 0 "register_operand" "=D") (plus:DI (match_dup 1) (const_int 8)))] - "TARGET_64BIT" + "TARGET_64BIT + && !(fixed_regs[AX_REG] || fixed_regs[DI_REG])" "stosq" [(set_attr "type" "str") (set_attr "memory" "store") @@ -15892,7 +15906,7 @@ (set (match_operand:P 0 "register_operand" "=D") (plus:P (match_dup 1) (const_int 4)))] - "" + "!(fixed_regs[AX_REG] || fixed_regs[DI_REG])" "stos{l|d}" [(set_attr "type" "str") (set_attr "memory" "store") @@ -15904,7 +15918,7 @@ (set (match_operand:P 0 "register_operand" "=D") (plus:P (match_dup 1) (const_int 2)))] - "" + "!(fixed_regs[AX_REG] || fixed_regs[DI_REG])" "stosw" [(set_attr "type" "str") (set_attr "memory" "store") @@ -15916,7 +15930,7 @@ (set (match_operand:P 0 "register_operand" "=D") (plus:P (match_dup 1) (const_int 1)))] - "" + "!(fixed_regs[AX_REG] || fixed_regs[DI_REG])" "stosb" [(set_attr "type" "str") (set_attr "memory" "store") @@ -15947,7 +15961,8 @@ (const_int 0)) (use (match_operand:DI 2 "register_operand" "a")) (use (match_dup 4))] - "TARGET_64BIT" + "TARGET_64BIT + && !(fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])" "rep{%;} stosq" [(set_attr "type" "str") (set_attr "prefix_rep" "1") @@ -15964,7 +15979,7 @@ (const_int 0)) (use (match_operand:SI 2 "register_operand" "a")) (use (match_dup 4))] - "" + "!(fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])" "rep{%;} stos{l|d}" [(set_attr "type" "str") (set_attr "prefix_rep" "1") @@ -15980,7 +15995,7 @@ (const_int 0)) (use (match_operand:QI 2 "register_operand" "a")) (use (match_dup 4))] - "" + "!(fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])" "rep{%;} stosb" [(set_attr "type" "str") (set_attr "prefix_rep" "1") @@ -16005,8 +16020,8 @@ if (optimize_insn_for_size_p () && !TARGET_INLINE_ALL_STRINGOPS) FAIL; - /* Can't use this if the user has appropriated esi or edi. */ - if (fixed_regs[SI_REG] || fixed_regs[DI_REG]) + /* Can't use this if the user has appropriated ecx, esi or edi. */ + if (fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG]) FAIL; out = operands[0]; @@ -16101,7 +16116,7 @@ (clobber (match_operand:P 0 "register_operand" "=S")) (clobber (match_operand:P 1 "register_operand" "=D")) (clobber (match_operand:P 2 "register_operand" "=c"))] - "" + "!(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])" "repz{%;} cmpsb" [(set_attr "type" "str") (set_attr "mode" "QI") @@ -16141,7 +16156,7 @@ (clobber (match_operand:P 0 "register_operand" "=S")) (clobber (match_operand:P 1 "register_operand" "=D")) (clobber (match_operand:P 2 "register_operand" "=c"))] - "" + "!(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])" "repz{%;} cmpsb" [(set_attr "type" "str") (set_attr "mode" "QI") @@ -16153,11 +16168,11 @@ (set_attr "prefix_rep" "1")]) (define_expand "strlen<mode>" - [(set (match_operand:SWI48x 0 "register_operand" "") - (unspec:SWI48x [(match_operand:BLK 1 "general_operand" "") - (match_operand:QI 2 "immediate_operand" "") - (match_operand 3 "immediate_operand" "")] - UNSPEC_SCAS))] + [(set (match_operand:P 0 "register_operand" "") + (unspec:P [(match_operand:BLK 1 "general_operand" "") + (match_operand:QI 2 "immediate_operand" "") + (match_operand 3 "immediate_operand" "")] + UNSPEC_SCAS))] "" { if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3])) @@ -16182,7 +16197,7 @@ (match_operand:P 4 "register_operand" "0")] UNSPEC_SCAS)) (clobber (match_operand:P 1 "register_operand" "=D")) (clobber (reg:CC FLAGS_REG))] - "" + "!(fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])" "repnz{%;} scasb" [(set_attr "type" "str") (set_attr "mode" "QI") @@ -17567,7 +17582,7 @@ (define_insn_and_split "*call_value_pop_1_vzeroupper" [(parallel [(set (match_operand 0 "" "") - (call (mem:QI (match_operand:SI 1 "call_insn_operand" "lsm")) + (call (mem:QI (match_operand:SI 1 "call_insn_operand" "lzm")) (match_operand:SI 2 "" ""))) (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) @@ -17583,7 +17598,7 @@ (define_insn "*call_value_pop_1" [(set (match_operand 0 "" "") - (call (mem:QI (match_operand:SI 1 "call_insn_operand" "lsm")) + (call (mem:QI (match_operand:SI 1 "call_insn_operand" "lzm")) (match_operand:SI 2 "" ""))) (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) @@ -17595,7 +17610,7 @@ (define_insn_and_split "*sibcall_value_pop_1_vzeroupper" [(parallel [(set (match_operand 0 "" "") - (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "s,U")) + (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "z,U")) (match_operand:SI 2 "" ""))) (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) @@ -17611,7 +17626,7 @@ (define_insn "*sibcall_value_pop_1" [(set (match_operand 0 "" "") - (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "s,U")) + (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "z,U")) (match_operand:SI 2 "" ""))) (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) @@ -17712,7 +17727,7 @@ (define_insn_and_split "*call_value_1_vzeroupper" [(set (match_operand 0 "" "") - (call (mem:QI (match_operand:SI 1 "call_insn_operand" "lsm")) + (call (mem:QI (match_operand:SI 1 "call_insn_operand" "lzm")) (match_operand:SI 2 "" ""))) (unspec [(match_operand 3 "const_int_operand" "")] UNSPEC_CALL_NEEDS_VZEROUPPER)] @@ -17725,7 +17740,7 @@ (define_insn "*call_value_1" [(set (match_operand 0 "" "") - (call (mem:QI (match_operand:SI 1 "call_insn_operand" "lsm")) + (call (mem:QI (match_operand:SI 1 "call_insn_operand" "lzm")) (match_operand:SI 2 "" "")))] "!TARGET_64BIT && !SIBLING_CALL_P (insn)" { return ix86_output_call_insn (insn, operands[1], 1); } @@ -17733,7 +17748,7 @@ (define_insn_and_split "*sibcall_value_1_vzeroupper" [(set (match_operand 0 "" "") - (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "s,U")) + (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "z,U")) (match_operand:SI 2 "" ""))) (unspec [(match_operand 3 "const_int_operand" "")] UNSPEC_CALL_NEEDS_VZEROUPPER)] @@ -17746,7 +17761,7 @@ (define_insn "*sibcall_value_1" [(set (match_operand 0 "" "") - (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "s,U")) + (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "z,U")) (match_operand:SI 2 "" "")))] "!TARGET_64BIT && SIBLING_CALL_P (insn)" { return ix86_output_call_insn (insn, operands[1], 1); } @@ -17754,7 +17769,7 @@ (define_insn_and_split "*call_value_1_rex64_vzeroupper" [(set (match_operand 0 "" "") - (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm")) + (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rzm")) (match_operand:DI 2 "" ""))) (unspec [(match_operand 3 "const_int_operand" "")] UNSPEC_CALL_NEEDS_VZEROUPPER)] @@ -17768,7 +17783,7 @@ (define_insn "*call_value_1_rex64" [(set (match_operand 0 "" "") - (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm")) + (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rzm")) (match_operand:DI 2 "" "")))] "TARGET_64BIT && !SIBLING_CALL_P (insn) && ix86_cmodel != CM_LARGE && ix86_cmodel != CM_LARGE_PIC" @@ -17778,7 +17793,7 @@ (define_insn_and_split "*call_value_1_rex64_ms_sysv_vzeroupper" [(parallel [(set (match_operand 0 "" "") - (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm")) + (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rzm")) (match_operand:DI 2 "" ""))) (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL) (clobber (reg:TI XMM6_REG)) @@ -17804,7 +17819,7 @@ (define_insn "*call_value_1_rex64_ms_sysv" [(set (match_operand 0 "" "") - (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm")) + (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rzm")) (match_operand:DI 2 "" ""))) (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL) (clobber (reg:TI XMM6_REG)) @@ -17846,7 +17861,7 @@ (define_insn_and_split "*sibcall_value_1_rex64_vzeroupper" [(set (match_operand 0 "" "") - (call (mem:QI (match_operand:DI 1 "sibcall_insn_operand" "s,U")) + (call (mem:QI (match_operand:DI 1 "sibcall_insn_operand" "z,U")) (match_operand:DI 2 "" ""))) (unspec [(match_operand 3 "const_int_operand" "")] UNSPEC_CALL_NEEDS_VZEROUPPER)] @@ -17859,7 +17874,7 @@ (define_insn "*sibcall_value_1_rex64" [(set (match_operand 0 "" "") - (call (mem:QI (match_operand:DI 1 "sibcall_insn_operand" "s,U")) + (call (mem:QI (match_operand:DI 1 "sibcall_insn_operand" "z,U")) (match_operand:DI 2 "" "")))] "TARGET_64BIT && SIBLING_CALL_P (insn)" { return ix86_output_call_insn (insn, operands[1], 1); } @@ -18270,8 +18285,8 @@ (match_operand:SI 3 "const_int_operand" "i")] UNSPECV_LWPVAL_INTRINSIC)] "TARGET_LWP" - "/* Avoid unused variable warning. */ - (void) operand0;") + ;; Avoid unused variable warning. + "(void) operands[0];") (define_insn "*lwp_lwpval<mode>3_1" [(unspec_volatile [(match_operand:SWI48 0 "register_operand" "r") |