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* Delete old versions of GCC.Dan Albert2015-06-171540-876955/+0
| | | | Change-Id: I710f125d905290e1024cbd67f48299861790c66c
* [gcc] Remove "-mstackrealign" option turned on by default on x86.Alexander Ivchenko2014-10-141-1/+1
| | | | | | | | For ndk docs change, please refer to: https://android-review.googlesource.com/#/c/110100/ Change-Id: Icbe13a158511d519312b2a1d3e606c9dd2bff4af Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
* [4.6,4.8,4.9] Neon2SSE porting solution updatePavel Chupin2014-09-121-3051/+11030
| | | | | | | | | | Improve NEON instrinsics coverage from ~41% to ~93%. This change brings new intrinsics and modifies old ones for better maintainability. Also take into account that IA32 now supports SSSE3 by default, so we can get rid of SSSE3 checks. Change-Id: I599c3b93dcf92d0c94bdb786a4aad705f075893b Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
* Setup x86_64 ABI and add -mssse3 to x86 ABIPavel Chupin2014-06-201-1/+1
| | | | | | | | | | | 32-bit: replace -msse3 by -mssse3 64-bit: setup default options as -msse4.2 -mpopcnt Note: when multilib compiler is used -m32 will match 32-bit options and -m64 or default (neither -m32 nor -m64) will match 64-bit options. Change-Id: Ia20a03f54e3ff5857108e9ab0ae1c4c7c1e6cc7f Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
* [4.6,4.8,4.9] Porting ARM NEON intrinsics to SSE x86Anton Konovalov2014-06-071-0/+8641
| | | | | | | | Added arm_neon.h to gcc 4.6, 4.8 and 4.9 toolchains. Updated config.gcc files. Change-Id: If9c12c3e31f5256b178816dffb41c86af0912db0 Signed-off-by: Anton Konovalov <anton.konovalov@intel.com> Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
* [4.6] Fix build of 4.6 compiler using newer 4.8. Backport of two patchesAlexander Ivchenko2014-05-228-21/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | from 4.6.4 release: 2012-09-21 Richard Guenther <rguenther@suse.de> PR middle-end/54638 Backport from mainline 2012-04-19 Richard Guenther <rguenther@suse.de> * ira-int.h (ira_allocno_object_iter_cond): Avoid out-of-bound array access. 2012-04-20 Thomas Schwinge <thomas@codesourcery.com> * config/alpha/linux-unwind.h (alpha_fallback_frame_state): Use siginfo_t instead of struct siginfo. * config/bfin/linux-unwind.h (bfin_fallback_frame_state): Likewise. * config/i386/linux-unwind.h (x86_fallback_frame_state): Likewise. * config/ia64/linux-unwind.h (ia64_fallback_frame_state) (ia64_handle_unwabi): Likewise. * config/mips/linux-unwind.h (mips_fallback_frame_state): Likewise. * config/pa/linux-unwind.h (pa32_fallback_frame_state): Likewise. * config/sh/linux-unwind.h (shmedia_fallback_frame_state) (sh_fallback_frame_state): Likewise. * config/xtensa/linux-unwind.h (xtensa_fallback_frame_state): Likewise. Change-Id: If84780aad73abf47ba08bef806ac0b728c4e1c02 Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
* Fix host 64-bit gcc4.6 buildAndrew Hsieh2014-03-051-1/+1
| | | | | | | | | | | | | | ANDROID_CC1_SPEC should be used with argument, otherwise it's not expanded and fail compilation. Note that we are not building 64-bit 4.6 target toolchain. 64-bit target toolchains are built from 4.7 and up instead. This issue only occurs when building 64-bit host compiler (x86_64), eg. aosp/prebuilts/gcc/linux-x86/host. The argument doesn't matter, although we put "-fPIC" to be consistent with its 32-bit counterpart Change-Id: I746b14a6e4471a4bd62fb4e29b574669d4b7a9d1
* [4.6, 4.8] Add additional multilib option: mfloat-abi=hardAndrew Hsieh2013-12-261-3/+4
| | | | | | | | | | | | Only available with "-march=armv7-a", this CL add two set of libraries 1. "armv7-a/hard": -march=armv7-a -mfloat-abi=hard 2. "armv7-a/thumb/hard": -march=armv7-a -mthumb -mfloat-abi=hard Note that -mhard-float implies -mfloat-abi=hard, which in turns select one of the above /hard libraries dependeing on the presence of -mthumb or not. (ie. no need to explicitly specifly -mfloat-abi=hard after -mhard-float) Change-Id: Ib803ecaa911082d6bc4f98b542d7d28e98be6726
* [4.6, 4.8] Add -mtune=intel supportPavel Chupin2013-12-092-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is backport of r205719 and r205754 from trunk. Now -mtune=intel matches -mtune=slm for 4.8 and -mtune=atom for 4.6. As written in gcc-4.8 docs: Produce code optimized for the most current Intel processors, which are Haswell and Silvermont for this version of GCC. If you know the CPU on which your code will run, then you should use the corresponding -mtune or -march option instead of -mtune=intel. But, if you want your application performs better on both Haswell and Silvermont, then you should use this option. As new Intel processors are deployed in the marketplace, the behavior of this option will change. Therefore, if you upgrade to a newer version of GCC, code generation controlled by this option will change to reflect the most current Intel processors at the time that version of GCC is released. There is no -march=intel option because -march indicates the instruction set the compiler can use, and there is no common instruction set applicable to all processors. In contrast, -mtune indicates the processor (or, in this case, collection of processors) for which the code is optimized. Change-Id: I3ec4c3b5423d9b3547cd8e3aa77a18af3fd89598 Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
* Extend MIPS GCC4.6/4.7/4.8 -mldc1-sdc1 to control ldxc1/sdxc1 tooIceberg Fu2013-08-302-3/+3
| | | | | | | | | | | | | -mldc1-sdc1 now also controls codegen of ldxc1/sdxc1, the indexed versions (where address of load/store is computed from sum of two registers) of ldc1/sdc1 which are already controlled by this option. Although double (or struct containing double) is always aligned and the stock does guarantee 8-byte alignment, this option is to workaround issue when double is allocated from a custom allocator w/o honoring 8-byte minimal alignment. Change-Id: I79433976509b885b5699d62693fd3154bb752abf
* Add MXU support in gcc4.6/4.7/4.8 with -mmxuAndrew Hsieh2013-08-152-0/+5
| | | | | | For Ingenic MXU. Change-Id: Ie7b465c971e3642b3244ac1a77b6f86be4ab4fea
* [4.6,4.7] Always enable --eh-frame-hdr for static executableAndrew Hsieh2013-08-074-1/+16
| | | | | | | See 23e3137ee2897464b051599b85a09f130d3ad05d for the reason why. backport 4.8 patch from http://gcc.gnu.org/ml/gcc-patches/2012-09/msg00969.html Change-Id: I9496e11f314e5e2ec9359b993016723ab6366dad
* Merge "Add an internal switch -minline-thumb1-jumptable to ARM gcc4.6/4.7/4.8"Andrew Hsieh2013-08-074-3/+9
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| * Add an internal switch -minline-thumb1-jumptable to ARM gcc4.6/4.7/4.8Lai Wei-Chih2013-08-024-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Default is off (ie. no changes of behavior), meaning that gcc may generate thumb1 jumptable helper calls (eg. __gnu_thumb1_case_sqi) for switch/case. Use -minline-thumb1-jumptable to compile code which can be linked with compiler-rt where helper __gnu_thumb1_case_* doesn't exist. This is mainly for use to compile NDK gabi++/stlport/libc++ to be independent of libgcc.a. The only affected binaries are all in armeabi. ABIs armeabi-v7a and x86/mips aren't affected. Size differences are libgabi++_static.a 176286 -> 176538 +0.1% libstlport_static.a 1406346 -> 1413318 +0.5% libc++_static.a 2426814 -> 2439074 +0.5% Change-Id: I582898955b28e53e988a91bc1a64b76fba677e58
* | [4.6,4.8] Add stack unwinding directives for __aeabi_idiv0 in libgcc.aAndrew Hsieh2013-08-031-0/+6
|/ | | | | | Same fix to 4.7 in 5ea1e88a7f14a78a01d95f66e388eb15908a5225 Change-Id: I1b2ce4ad72e6b2a327183703d9e49295cf2bad25
* Fix gcc4.6 thumb2 fails to generate 16bit relative jump tableAndrew Hsieh2013-07-241-1/+1
| | | | | | | | | 2011-08-12 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org> PR target/48328 * config/arm/arm.h (CASE_VECTOR_SHORTEN_MODE): Fix distance for tbh instructions. Change-Id: Ic269b2a12c727059714ef7653bc63eaccfd74f90
* Fix GCC 4.6 ARM broken -Os on boost 1.52.0Andrew Hsieh2013-06-211-4/+4
| | | | | | | | | | | | | | | | | See b.andriod.com/42891 Back port r190971 2012-09-05 Bin Cheng <bin.cheng@arm.com> Backport from 2012-09-04 mainline r190919 PR target/45070 * config/arm/arm.c (thumb1_extra_regs_pushed): Handle return value of size less than 4 bytes by using macro ARM_NUM_INTS. (thumb1_unexpanded_epilogue): Use macro ARM_NUM_INTS. Change-Id: Ib43bc77abae8d487e82802c8c1f1cce87d5a7e5e
* Add new GCC/MIPS option -mldc1-sdc1Andrew Hsieh2013-04-262-1/+5
| | | | | | | | ldc1/sdc1 needs memory to be 8-byte aligned. This option is on by default for arch supports it, but can be turned off by "-mno-ldc1-sdc1" to workaround issue, for example. Change-Id: I14291dc4280e75f6c765c933b60eb1b7cd44f974
* Fix GCC4.4.3/4.6/4.7 to supress -export-dynamic for statically linked programsAndrew Hsieh2013-04-121-2/+3
| | | | | | | | | r191401 | jingyu | 2012-09-18 01:33:05 +0800 (Tue, 18 Sep 2012) | 6 lines 2012-09-17 Ben Cheng <bccheng@google.com * config/arm/linux-elf.h (LINUX_TARGET_LINK_SPEC): Suppress the dynamic linker commands for statically linked programs. Change-Id: Ib8a27fb054ddb12242d500ef8b3ceb2b0215cb3e
* Misc fixesAndrew Hsieh2013-04-041-1/+1
| | | | | | | | | | 1. Fixed darwin build of GCC 4.8/X86 by removing trailing ',' from the last item of enum. Not discovered before because GCC 4.8 now builds with -Wall -Werror, and gcc-4.2.1 in darwin is picky about that 2. Fixed -fuse-ld=mcld Change-Id: I7b65edfb76841f14c3290acb5a98f556d00e1139
* Fixed GCC 4.6/4.7 ICE gen_thumb_movhi_clobber at config/arm/arm.md:5832Andrew Hsieh2013-03-052-1/+2
| | | | | | | See issue https://code.google.com/p/android/issues/detail?id=52732, and fix http://gcc.gnu.org/ml/gcc-patches/2010-12/msg00732.html Change-Id: If4759a637e5fb6f9c351c11b79d7f9f682ca2ab2
* Fix MIPS GCC to emit -m elf32ltsmip for linkerAndrew Hsieh2013-02-281-0/+1
| | | | | | | | | | ARM/X86 GCC in NDK explicitly emit -m armelf_linux_eabi and -m elf_i386, respectively, for linker. Fix MIPS to do the same, to help mclinker which is built vanilla and relies on either filename (eg. eg. arm-linux-androideabi-ld.mcd implies arm) or -mtriple/-march/-m to figure out the target Change-Id: I236786d0e90a3152225de1eea5e73e3de4ac3f84
* Use memalign instead of posix_memalign in GCC x86 mm_malloc.hAndrew Hsieh2013-02-201-0/+6
| | | | | | | | | | | | | | posix_memalign doesn't exist in NDK. Code inludes ?mmintrin.h which in turn includes mm_malloc.h may fail to link For AOSP platform build which uses the same compiler, add -DHAVE_POSIX_MEMALIGN to restore the original behavior. Other than non-zero return value which _mm_alloc already ignores, both paths are functioanlly identical (under the hood dlmalloc.c in 32-bit ensure alignment is at least 16-byte) Change-Id: I55e9bb8b80e1b55baa9744920df10fcf83218300
* Remove march/mtune/mfpmath hardcoded valuesPavel Chupin2013-01-311-2/+1
| | | | | | | | They should be passed in configure to work correctly. See https://android-review.googlesource.com/50815 Change-Id: I2aeb0375132ba985a51c397ee386af1ff4a47c32 Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
* Fix OpenMPAndrew Hsieh2012-12-276-11/+15
| | | | | | | | | | | | | | Based on 1271761f530c0050154e8d526b95f952df551751, 92c478dba755a1a2f6f00ff390666acbffd41982, and 51df2e98d22e2c6f5d2a16860bc8fc3644179c1d. With the following modifications: 1. Translate -pthread to -lc instead of -lpthread Android doesn't have (has pthread* in libc.so instead) 2. Because of 1., we can restore to the original order of LINUX_OR_ANDROID_LD Change-Id: I505250c32b9908cb17bb269dc26e73c91669c07f
* Support OpenMP for task parallelism on Android-ICS/GCC-4.6.3Geunsik Lim2012-12-252-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch supports OpenMP library to parallelize the existing C/C++ code rapidly/easily without any modification of android platform on multicore embedded devices. The original patch is made by Keith Obenschain (using GCC 4.4.3). .Archive - https://android-review.googlesource.com/#/c/34491/ I just moved GCC version from 4.4.3 to 4.6.3 for ktoolchain version 2.5. The patch is good to me when I evaluate a lot of C/C++ source code with OpenMP's #parama. Please, refer to the "kandroid toolchain" menu in www.kandroid.org to compile source code including bionic and openmp library on real Android devices. http://kandroid.org/board/board.php?board=toolchain&command=body&no=16 I tested Openmp library with the latest GCC 4.6.3 on Android/ARM devices as following. Please refer to the below example. geunsik@invain-rhel6$> ./arm-linux-androideabi-gcc openmptest.c -L /usr/local/ktoolchain-cortexa9-ver2.5-bionic/ arm-linux-androideabi/lib -lgomp -o openmptest [ENTER] geunsik@invain-rhel6$> geunsik@invain-rhel6$> geunsik@invain-rhel6$> file ./openmptest ./openmptest: ELF 32-bit LSB executable, ARM, version 1 (SYSV), dynamically linked (uses shared libs), not stripped Change-Id: I55b6a6c2205c09dd6b923f9da07b185167145e87 Signed-off-by: Geunsik Lim <leemgs@gmail.com> Acked-by: Geunsik Lim <geunsik.lim@gmail.com> Acked-by: Geunsik Lim <geunsik.lim@samsung.com>
* Fix ARM GCC 4.6/4.7 fail to links code using 64-bit atomic built-inAndrew Hsieh2012-12-121-0/+4
| | | | | | | | | | For ARM w/o dmb a helper function is called for 64-bit atomic built-in, which call __write when helper version is too old. Change to call write instead for Android. See http://code.google.com/p/android/issues/detail?id=41297 Change-Id: I98218576c5223628c0c76870623788f07675f6e5
* Enable MIPS floating-point madd/msub/nmadd/nmsub/recip/rsqrt with 32-bit FPU.Chao-ying Fu2012-12-112-9/+4
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* Fix GCC 4.6 ARM ICE at reload1.c:1061Andrew Hsieh2012-12-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | See http://code.google.com/p/android/issues/detail?id=20862 Disable r172951 in -O0 to fix issue. r172951 optimizes the case when the estimated funciton size is small, all branches in funciton become short jump, ie. the function doesn't contain far jump which clobber register "lr". Unfortunately the estimation may not be correct before register allocation because spill code may increase the function size and invalidate the assumption about whether to save/restore "lr" or not. Fortunately, "lr" is already save/restored when the funciton use r4-r7 or contains spill code. r172951 works because register allocator must exhaust r4-r7 before spill code, so the size estimation when r4-r7 are NOT used is accurate. Unfortunately this isn't the case in -O0 when compiler doesn't use r4-r7 at all yet somehow the size estimation is wrong. Disable it for -O0 r172951 | carrot | 2011-04-26 09:55:33 +0800 (Tue, 26 Apr 2011) | 5 lines * gcc/config/arm/arm.c (SHORTEST_FAR_JUMP_LENGTH): New constant. (estimate_function_length): New function. (thumb_far_jump_used_p): No far jump is needed in short function. Change-Id: I0973d2141787332fc61501fbe76dc7c44c9d1282
* Backport 64-bit built-in atomic functions for ARM to GCC 4.6Andrew Hsieh2012-11-227-304/+490
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | r179983 | rsandifo | 2011-10-14 22:39:32 +0800 (Fri, 14 Oct 2011) | 12 lines 2011-10-14 David Alan Gilbert <david.gilbert@linaro.org> * gcc.dg/di-longlong64-sync-1.c: New test. * gcc.dg/di-sync-multithread.c: New test. * gcc.target/arm/di-longlong64-sync-withhelpers.c: New test. * gcc.target/arm/di-longlong64-sync-withldrexd.c: New test. * lib/target-supports.exp: (arm_arch_*_ok): Series of effective-target tests for v5, v6, v6k, and v7-a, and add-options helpers. (check_effective_target_arm_arm_ok): New helper. (check_effective_target_sync_longlong): New helper. r179982 | rsandifo | 2011-10-14 22:39:10 +0800 (Fri, 14 Oct 2011) | 8 lines 2011-10-14 David Alan Gilbert <david.gilbert@linaro.org> * config/arm/linux-atomic-64bit.c: New (based on linux-atomic.c). * config/arm/linux-atomic.c: Change comment to point to 64bit version. (SYNC_LOCK_RELEASE): Instantiate 64bit version. * config/arm/t-linux-eabi: Pull in linux-atomic-64bit.c. r179981 | rsandifo | 2011-10-14 22:38:58 +0800 (Fri, 14 Oct 2011) | 44 lines 2011-10-14 David Alan Gilbert <david.gilbert@linaro.org> * config/arm/arm.c (arm_output_ldrex): Support ldrexd. (arm_output_strex): Support strexd. (arm_output_it): New helper to output it in Thumb2 mode only. (arm_output_sync_loop): Support DI mode. Change comment to not support const_int. (arm_expand_sync): Support DI mode. * config/arm/arm.h (TARGET_HAVE_LDREXBHD): Split into LDREXBH and LDREXD. * config/arm/iterators.md (NARROW): move from sync.md. (QHSD): New iterator for all current ARM integer modes. (SIDI): New iterator for SI and DI modes only. * config/arm/sync.md (sync_predtab): New mode_attr. (sync_compare_and_swapsi): Fold into sync_compare_and_swap<mode>. (sync_lock_test_and_setsi): Fold into sync_lock_test_and_setsi<mode>. (sync_<sync_optab>si): Fold into sync_<sync_optab><mode>. (sync_nandsi): Fold into sync_nand<mode>. (sync_new_<sync_optab>si): Fold into sync_new_<sync_optab><mode>. (sync_new_nandsi): Fold into sync_new_nand<mode>. (sync_old_<sync_optab>si): Fold into sync_old_<sync_optab><mode>. (sync_old_nandsi): Fold into sync_old_nand<mode>. (sync_compare_and_swap<mode>): Support SI & DI. (sync_lock_test_and_set<mode>): Likewise. (sync_<sync_optab><mode>): Likewise. (sync_nand<mode>): Likewise. (sync_new_<sync_optab><mode>): Likewise. (sync_new_nand<mode>): Likewise. (sync_old_<sync_optab><mode>): Likewise. (sync_old_nand<mode>): Likewise. (arm_sync_compare_and_swapsi): Turn into iterator on SI & DI. (arm_sync_lock_test_and_setsi): Likewise. (arm_sync_new_<sync_optab>si): Likewise. (arm_sync_new_nandsi): Likewise. (arm_sync_old_<sync_optab>si): Likewise. (arm_sync_old_nandsi): Likewise. (arm_sync_compare_and_swap<mode> NARROW): use sync_predtab, fix indent. (arm_sync_lock_test_and_setsi<mode> NARROW): Likewise. (arm_sync_new_<sync_optab><mode> NARROW): Likewise. (arm_sync_new_nand<mode> NARROW): Likewise. (arm_sync_old_<sync_optab><mode> NARROW): Likewise. (arm_sync_old_nand<mode> NARROW): Likewise. r179980 | rsandifo | 2011-10-14 22:38:42 +0800 (Fri, 14 Oct 2011) | 6 lines 2011-10-14 David Alan Gilbert <david.gilbert@linaro.org> PR target/48126 * config/arm/arm.c (arm_output_sync_loop): Move label before barrier. r179979 | rsandifo | 2011-10-14 22:38:30 +0800 (Fri, 14 Oct 2011) | 5 lines 2011-10-14 David Alan Gilbert <david.gilbert@linaro.org> * config/arm/arm.h (TARGET_HAVE_DMB_MCR): MCR Not available in Thumb1. Change-Id: Ic27fcf0b49e835cefdafb24fbba2f6023059d2b3
* Add -mstack-protector-guard= to x86 compilersAndrew Hsieh2012-11-014-4/+33
| | | | | | | | | | | | | | | | | | | | To choose between "global" (default) and "tls" (new) for -fstack-protector, -fstack-protector-all, and -fstack-protector-strong (GCC 4.6+). Note that this alone doesn't enable any -fstack-protector* For NDK: The default "global" generates code backward compatible with older bionic For AOSP: build may add "-mstack-protector-guard=tls" to build platform code with new bionic (*1) Related CL: https://android-review.googlesource.com/#/c/45416 (*1) https://android-review.googlesource.com/#/c/45784 Change-Id: Iedf5b7ae5148572db2e35f0add93bc3d13511304
* Return to %gs:20 code generation for -fstack-protector on x86Pavel Chupin2012-10-301-4/+4
| | | | | | | | | After https://android-review.googlesource.com/#/c/45416 bionic provides stack-protector random value per each thread at %gs:20. Therefore return compiler back to %gs:20 code gen, same as for glibc. Change-Id: I76c68f0c99846d247f34e0ea781a7f1c305659b9 Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
* Merge "Port MIPS Android support to GCC-4.6/4.7"Andrew Hsieh2012-10-232-11/+44
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| * Port MIPS Android support to GCC-4.6/4.7Andrew Hsieh2012-10-232-11/+44
| | | | | | | | | | | | | | Used to be local NDK patch at $NDK/build/tools/toolchain-patches/ gcc/0008-Port-MIPS-Android-support-to-GCC-4.6.patch Change-Id: I486ea194683b370dcb038488a92fadef7e2da1ac
* | Merge "Enable x86/arm gcc defaults"Andrew Hsieh2012-10-233-4/+12
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| * Enable x86/arm gcc defaultsAndrew Hsieh2012-10-233-4/+12
| | | | | | | | | | | | | | Used to be local NDK patch at $NDK/build/tools/toolchain-patches/ gcc/0004-Enable-x86-gcc-defaults.patch Change-Id: I6cb6ba8b29b7ba4f242f788a57bf0460289f0cbd
* | Enable assembler linker default for securityAndrew Hsieh2012-10-235-5/+17
|/ | | | | | | Used to be local NDK patch at $NDK/build/tools/toolchain-patches/ gcc/0009-Enable-assembler-linker-default-for-security.patch Change-Id: I0211ee770e9d4db036361390fcb5892d4e39356f
* Fix MIPS GCC __builtin_unreachable issue compiling LLVMAndrew Hsieh2012-09-061-1/+4
| | | | | | | See Bug 54369: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54369 Change-Id: I1a84f7c95e05e26b2906e79947a43f64d5621362
* Disable warning: the mangling of <va_list> has changed in GCC 4.4Andrew Hsieh2012-08-281-0/+13
| | | | | | | | | | | | | | | | | | | | Disable this obsolete warning for Android, because none of the exposed APIs NDK is impacted by this change of ARM ABI. This warning can be triggered very easily by compiling the following code using arm-linux-androideabi-g++: typedef __builtin_va_list __gnuc_va_list; typedef __gnuc_va_list va_list; void foo(va_list v) { } We could advise developer to add "-Wno-psabi", but doing so also categorically deny other cases guarded by "warn_psabi". Hence the decision to disable it case by case here. Related discussion: https://groups.google.com/d/msg/android-ndk/-/7XLgL08iv0sJ Change-Id: I2c5c42e4593d3a1806f7840ccaa3e59d8d1c2315
* Backport from trunk r190598 and r190599: 64-bit long double for bionicPavel Chupin2012-08-244-4/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2012-08-22 H.J. Lu <hongjiu.lu@intel.com> Replace REAL_VALUE_TO_TARGET_LONG_DOUBLE with real_to_target PR target/54347 * config/i386/i386.c (ix86_split_to_parts): Replace REAL_VALUE_TO_TARGET_LONG_DOUBLE with real_to_target. 2012-08-22 H.J. Lu <hongjiu.lu@intel.com> Add -mlong-double-64/-mlong-double-80 to i386 gcc/ * doc/invoke.texi: Document -mlong-double-64/-mlong-double-80. * config/i386/i386.c (flag_opts): Add -mlong-double-64. (TARGET_HAS_BIONIC): Default long double to 64-bit for Bionic. * config/i386/i386.h (LONG_DOUBLE_TYPE_SIZE): Use 64 if TARGET_LONG_DOUBLE_64 is true. (LIBGCC2_LONG_DOUBLE_TYPE_SIZE): New macro. (WIDEST_HARDWARE_FP_SIZE): Defined to 80. * config/i386/i386.opt (mlong-double-80): New option. (mlong-double-64): Likewise. * config/i386/i386-c.c (ix86_target_macros): Define __LONG_DOUBLE_64__ for TARGET_LONG_DOUBLE_64. gcc/testsuite/ * gcc.target/i386/long-double-64-1.c: New file. * gcc.target/i386/long-double-64-2.c: Likewise. * gcc.target/i386/long-double-64-3.c: Likewise. * gcc.target/i386/long-double-64-4.c: Likewise. * gcc.target/i386/long-double-80-1.c: Likewise. * gcc.target/i386/long-double-80-2.c: Likewise. * gcc.target/i386/long-double-80-3.c: Likewise. * gcc.target/i386/long-double-80-4.c: Likewise. * gcc.target/i386/long-double-80-5.c: Likewise. * gcc.target/i386/long-double-80-6.c: Likewise. * gcc.target/i386/long-double-80-7.c: Likewise. libgcc/ * config/i386/t-linux (HOST_LIBGCC2_CFLAGS): New. Change-Id: I85b1e7105e24272e6d43115797b4914b93c2a598 Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
* Add correct predicates.md for previous commitAndrew Hsieh2012-08-161-2/+5
| | | | | | | Add Correct predicates.md for previous commit 7e597b08eb15a88ef0e309f2e59df18a636b0c40. Change-Id: I3047d5276318d3b6fbf66e4c45d0a2f55978ff64
* Fix ARM internal compiler error reload1.c:3633 compiling EarthAndrew Hsieh2012-08-163-5/+18
| | | | | | | | | | | | | | ARM GCC 4.6 experiences ICE when compiles Earth in debug build libs/evll/database/quadtreecachetype.cc:237:1: internal compiler error: in elimination_costs_in_insn, at reload1.c:3633 The reason is that ARM back-end expects wrong operand type sign-extend from char. Back port fix from http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50099 Change-Id: Ia235b76c6f0bada472a741a763d087789a41db8e
* Backport from trunk r189840: stack-protector runtime fixPavel Chupin2012-08-062-4/+8
| | | | | | | | | | | | | | | | | | | | | | 2012-07-25 Sergey Melnikov <sergey.melnikov@intel.com> * config/i386/i386.md (stack_protect_set): Disable the pattern for Android since Android libc (bionic) does not provide random value for stack protection guard at gs:0x14. Guard value will be provided from external symbol (default implementation). (stack_protect_set_<mode>): Likewise. (stack_protect_test): Likewise. (stack_protect_test_<mode>): Likewise. * gcc/defaults.h: Define macro TARGET_HAS_BIONIC to 0 - target * does not have Bionic by default * config/linux.h: Redefine macro TARGET_HAS_BIONIC to * (OPTION_BIONIC) Macro OPTION_BIONIC is defined in this file and provides Bionic accessibility status Change-Id: I56ae8fd7fef7c21977072e7f3c24b93030f0b813 Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
* 2012-05-07 Jing Yu <jingyu@google.com>Jing Yu2012-05-073-16/+66
| | | | | | | | | | | | | | | | | | | | | | Backport r186560 and r185958 from gcc trunk 2012-05-03 Enkovich Ilya <ilya.enkovich@intel.com> * config/linux-android.h (ANDROID_STARTFILE_SPEC): Fix shared case. (ANDROID_ENDFILE_SPEC): Likewise. * config/i386/linux.h (TARGET_OS_CPP_BUILTINS): Add Android builtins. (LINUX_TARGET_CC1_SPEC): New. (CC1_SPEC): Support Android. (LINUX_TARGET_LINK_SPEC): New. (LINK_SPEC): Support Android. (LIB_SPEC): New. (STARTFILE_SPEC): New. (LINUX_TARGET_ENDFILE_SPEC): New. (ENDFILE_SPEC): Support Android. * config/i386/linux64.h: Likewise. Change-Id: I0cda19435822a3a3bb0ef1ece16ce0b282a0322b
* .init_array/.fini_array patch for Android/x86Jing Yu2012-02-221-0/+41
| | | | Backport from gcc mainline r177933, r175181, r177963, r178116, r183299.
* Sync down FSF r184235@google/gcc-4_6_2-mobile branchJing Yu2012-02-1548-544/+1949
| | | | | | | | 1) Get mostly new patches from FSF gcc-4.6 branch 2) Fix PR52129 3) Insert GNU-stack note for all ARM targets Change-Id: I2b9926981210e517e4021242908074319a91d6bd
* Add gcc-4.6. Synced to @180989Jing Yu2011-12-191536-0/+858447
Change-Id: Ie3676586e1d8e3c8cd9f07d022f450d05fa08439 svn://gcc.gnu.org/svn/gcc/branches/google/gcc-4_6-mobile
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