added boot script files to repository

8 files changed, 957 insertions, 0 deletions

diff --git a/u-boot/board/davedenx/aria/Makefile b/u-boot/board/davedenx/aria/Makefile
new file mode 100644
index 0000000..30dba23
--- /dev/null
+++ b/u-boot/board/davedenx/aria/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= $(BOARD).o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/davedenx/aria/aria.c b/u-boot/board/davedenx/aria/aria.c
new file mode 100644
index 0000000..31b079b
--- /dev/null
+++ b/u-boot/board/davedenx/aria/aria.c
@@ -0,0 +1,195 @@
+/*
+ * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+ * (C) Copyright 2009 Dave Srl www.dave.eu
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/mpc512x.h>
+#include <fdt_support.h>
+#ifdef CONFIG_MISC_INIT_R
+#include <i2c.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Clocks in use */
+#define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |				\
+			 CLOCK_SCCR1_LPC_EN |				\
+			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |	\
+			 CLOCK_SCCR1_PSCFIFO_EN |			\
+			 CLOCK_SCCR1_DDR_EN |				\
+			 CLOCK_SCCR1_FEC_EN |				\
+			 CLOCK_SCCR1_NFC_EN |				\
+			 CLOCK_SCCR1_PATA_EN |				\
+			 CLOCK_SCCR1_PCI_EN |				\
+			 CLOCK_SCCR1_TPR_EN)
+
+#define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_MEM_EN |		\
+			 CLOCK_SCCR2_SPDIF_EN |		\
+			 CLOCK_SCCR2_DIU_EN |		\
+			 CLOCK_SCCR2_I2C_EN)
+
+int board_early_init_f(void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 spridr;
+
+	/*
+	 * Initialize Local Window for the On Board FPGA access
+	 */
+	out_be32(&im->sysconf.lpcs2aw,
+		CSAW_START(CONFIG_SYS_ARIA_FPGA_BASE) |
+		CSAW_STOP(CONFIG_SYS_ARIA_FPGA_BASE, CONFIG_SYS_ARIA_FPGA_SIZE)
+	);
+	out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
+	sync_law(&im->sysconf.lpcs2aw);
+
+	/*
+	 * Initialize Local Window for the On Board SRAM access
+	 */
+	out_be32(&im->sysconf.lpcs6aw,
+		CSAW_START(CONFIG_SYS_ARIA_SRAM_BASE) |
+		CSAW_STOP(CONFIG_SYS_ARIA_SRAM_BASE, CONFIG_SYS_ARIA_SRAM_SIZE)
+	);
+	out_be32(&im->lpc.cs_cfg[6], CONFIG_SYS_CS6_CFG);
+	sync_law(&im->sysconf.lpcs6aw);
+
+	/*
+	 * Configure Flash Speed
+	 */
+	out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
+
+	spridr = in_be32(&im->sysconf.spridr);
+
+	if (SVR_MJREV(spridr) >= 2)
+		out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
+
+	/*
+	 * Enable clocks
+	 */
+	out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
+	out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
+#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
+	setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
+#endif
+
+	return 0;
+}
+
+phys_size_t initdram (int board_type)
+{
+	return fixed_sdram(NULL, NULL, 0);
+}
+
+int misc_init_r(void)
+{
+	u32 tmp;
+
+	/* we use I2C-2 for on-board eeprom */
+	i2c_set_bus_num(2);
+
+	tmp = in_be32((u32*)CONFIG_SYS_ARIA_FPGA_BASE);
+	printf("FPGA:  %u-%u.%u.%u\n",
+		(tmp & 0xFF000000) >> 24,
+		(tmp & 0x00FF0000) >> 16,
+		(tmp & 0x0000FF00) >>  8,
+		 tmp & 0x000000FF
+	);
+
+	return 0;
+}
+
+static  iopin_t ioregs_init[] = {
+	/*
+	 * FEC
+	 */
+
+	/* FEC on PSCx_x*/
+	{
+		offsetof(struct ioctrl512x, io_control_psc0_0), 5, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	{
+		offsetof(struct ioctrl512x, io_control_psc1_0), 10, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	{
+		offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+
+	/*
+	 * DIU
+	 */
+	/* FUNC2=DIU CLK */
+	{
+		offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
+	},
+	/* FUNC2=DIU_HSYNC */
+	{
+		offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
+	{
+		offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/*
+	 * On board SRAM
+	 */
+	/* FUNC2=/LPC CS6 */
+	{
+		offsetof(struct ioctrl512x, io_control_j1850_rx), 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(1) | IO_PIN_ST(1) | IO_PIN_DS(3)
+	},
+};
+
+int checkboard (void)
+{
+	puts("Board: ARIA\n");
+
+	/* initialize function mux & slew rate IO inter alia on IO Pins  */
+
+	iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/u-boot/board/davedenx/qong/Makefile b/u-boot/board/davedenx/qong/Makefile
new file mode 100644
index 0000000..1dca60d
--- /dev/null
+++ b/u-boot/board/davedenx/qong/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2009
+# Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= qong.o fpga.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/u-boot/board/davedenx/qong/config.mk b/u-boot/board/davedenx/qong/config.mk
new file mode 100644
index 0000000..ea1c1b0
--- /dev/null
+++ b/u-boot/board/davedenx/qong/config.mk
@@ -0,0 +1,3 @@
+CONFIG_SYS_TEXT_BASE = 0xa0000000
+
+# PLATFORM_CPPFLAGS += -DDEBUG
diff --git a/u-boot/board/davedenx/qong/fpga.c b/u-boot/board/davedenx/qong/fpga.c
new file mode 100644
index 0000000..656d5cd
--- /dev/null
+++ b/u-boot/board/davedenx/qong/fpga.c
@@ -0,0 +1,94 @@
+/*
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+#include <mxc_gpio.h>
+#include <fpga.h>
+#include <lattice.h>
+#include "qong_fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_FPGA)
+
+static void qong_jtag_init(void)
+{
+	return;
+}
+
+static void qong_fpga_jtag_set_tdi(int value)
+{
+	mxc_gpio_set(QONG_FPGA_TDI_PIN, value);
+}
+
+static void qong_fpga_jtag_set_tms(int value)
+{
+	mxc_gpio_set(QONG_FPGA_TMS_PIN, value);
+}
+
+static void qong_fpga_jtag_set_tck(int value)
+{
+	mxc_gpio_set(QONG_FPGA_TCK_PIN, value);
+}
+
+static int qong_fpga_jtag_get_tdo(void)
+{
+	return mxc_gpio_get(QONG_FPGA_TDO_PIN);
+}
+
+lattice_board_specific_func qong_fpga_fns = {
+	qong_jtag_init,
+	qong_fpga_jtag_set_tdi,
+	qong_fpga_jtag_set_tms,
+	qong_fpga_jtag_set_tck,
+	qong_fpga_jtag_get_tdo
+};
+
+Lattice_desc qong_fpga[CONFIG_FPGA_COUNT] = {
+	{
+		Lattice_XP2,
+		lattice_jtag_mode,
+		356519,
+		(void *) &qong_fpga_fns,
+		NULL,
+		0,
+		"lfxp2_5e_ftbga256"
+	},
+};
+
+int qong_fpga_init(void)
+{
+	int i;
+
+	fpga_init();
+
+	for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
+		fpga_add(fpga_lattice, &qong_fpga[i]);
+	}
+	return 0;
+}
+
+#endif
diff --git a/u-boot/board/davedenx/qong/lowlevel_init.S b/u-boot/board/davedenx/qong/lowlevel_init.S
new file mode 100644
index 0000000..80bed92
--- /dev/null
+++ b/u-boot/board/davedenx/qong/lowlevel_init.S
@@ -0,0 +1,236 @@
+/*
+ * Copyright (C) 2009, Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
+ *
+ * Based on board/freescale/mx31ads/lowlevel_init.S
+ * by Guennadi Liakhovetski.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/mx31-regs.h>
+
+.macro REG reg, val
+	ldr r2, =\reg
+	ldr r3, =\val
+	str r3, [r2]
+.endm
+
+.macro REG8 reg, val
+	ldr r2, =\reg
+	ldr r3, =\val
+	strb r3, [r2]
+.endm
+
+.macro DELAY loops
+	ldr r2, =\loops
+1:
+	subs	r2, r2, #1
+	nop
+	bcs 1b
+.endm
+
+.macro SETUP_RAM cfg, ctl
+	/* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
+	REG	0xB8001010, 0x00000004
+	ldr r3, =\cfg
+	ldr r2, =WEIM_ESDCFG0
+	str r3, [r2]
+	REG	0xB8001000, 0x92100000
+	REG	0x80000f00, 0x12344321
+	REG	0xB8001000, 0xa2100000
+	REG	0x80000000, 0x12344321
+	REG	0x80000000, 0x12344321
+	REG	0xB8001000, 0xb2100000
+	REG8	0x80000033, 0xda
+	REG8	0x81000000, 0xff
+	ldr r3, =\ctl
+	ldr r2, =WEIM_ESDCTL0
+	str r3, [r2]
+	REG	0x80000000, 0xDEADBEEF
+	REG	0xB8001010, 0x0000000c
+
+.endm
+/* RedBoot: To support 133MHz DDR */
+.macro init_drive_strength
+	/*
+	 * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
+	 * in SW_PAD_CTL registers
+	 */
+
+	/* SDCLK */
+	ldr r1, =IOMUXC_SW_PAD_CTL(0x2b)
+	ldr r0, [r1, #0x6C]
+	bic r0, r0, #(1 << 12)
+	str r0, [r1, #0x6C]
+
+	/* CAS */
+	ldr r0, [r1, #0x70]
+	bic r0, r0, #(1 << 22)
+	str r0, [r1, #0x70]
+
+	/* RAS */
+	ldr r0, [r1, #0x74]
+	bic r0, r0, #(1 << 2)
+	str r0, [r1, #0x74]
+
+	/* CS2 (CSD0) */
+	ldr r0, [r1, #0x7C]
+	bic r0, r0, #(1 << 22)
+	str r0, [r1, #0x7C]
+
+	/* DQM3 */
+	ldr r0, [r1, #0x84]
+	bic r0, r0, #(1 << 22)
+	str r0, [r1, #0x84]
+
+	/* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
+	ldr r2, =22	/* (0x2E0 - 0x288) / 4 = 22 */
+pad_loop:
+	ldr r0, [r1, #0x88]
+	bic r0, r0, #(1 << 22)
+	bic r0, r0, #(1 << 12)
+	bic r0, r0, #(1 << 2)
+	str r0, [r1, #0x88]
+	add r1, r1, #4
+	subs r2, r2, #0x1
+	bne pad_loop
+.endm /* init_drive_strength */
+
+.globl lowlevel_init
+lowlevel_init:
+
+	init_drive_strength
+
+	/* Image Processing Unit: */
+	/* Too early to switch display on? */
+	/* Switch on Display Interface */
+	REG	IPU_CONF, IPU_CONF_DI_EN
+	/* Clock Control Module: */
+	REG	CCM_CCMR, 0x074B0BF5		/* Use CKIH, MCU PLL off */
+
+	DELAY 0x40000
+
+	REG	CCM_CCMR, 0x074B0BF5 | CCMR_MPE			/* MCU PLL on */
+	/* Switch to MCU PLL */
+	REG	CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
+
+	/* 399-133-66.5 */
+	ldr	r0, =CCM_BASE
+	ldr	r1, =0xFF871650
+	/* PDR0 */
+	str	r1, [r0, #0x4]
+	ldr	r1, MPCTL_PARAM_399
+	/* MPCTL */
+	str	r1, [r0, #0x10]
+
+	/* Set UPLL=240MHz, USB=60MHz */
+	ldr	r1, =0x49FCFE7F
+	/* PDR1 */
+	str	r1, [r0, #0x8]
+	ldr	r1, UPCTL_PARAM_240
+	/* UPCTL */
+	str	r1, [r0, #0x14]
+	/* default CLKO to 1/8 of the ARM core */
+	mov	r1, #0x00000208
+	/* COSR */
+	str	r1, [r0, #0x1c]
+
+	/* Default: 1, 4, 12, 1 */
+	REG	CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
+
+check_ddr_module:
+/* Set stackpointer in internal RAM to call get_ram_size */
+	ldr	sp, =(IRAM_BASE_ADDR + IRAM_SIZE - 16)
+	stmfd	sp!, {r0-r11, ip, lr}
+	mov	ip, lr		/* save link reg across call */
+
+	ldr	r0,=0x08000000
+	SETUP_RAM	ESDCFG0_256MB, ESDCTL0_256MB
+	ldr	r0,=0x80000000
+	ldr	r1,=0x10000000
+	bl	get_ram_size
+	ldr	r1,=0x10000000
+	cmp	r0,r1
+	beq	restore_regs
+	SETUP_RAM	ESDCFG0_128MB, ESDCTL0_128MB
+	ldr	r0,=0x80000000
+	ldr	r1,=0x08000000
+	bl	get_ram_size
+	ldr	r1,=0x08000000
+	cmp	r0,r1
+	beq	restore_regs
+
+restore_regs:
+	ldmfd	sp!, {r0-r11, ip, lr}
+	mov	lr, ip		/* restore link reg */
+
+	mov	pc, lr
+
+
+MPCTL_PARAM_399:
+	.word (((1 - 1) << 26) + ((52 - 1) << 16) + (7 << 10) + (35 << 0))
+UPCTL_PARAM_240:
+	.word (((2 - 1) << 26) + ((13 - 1) << 16) + (9 << 10) + (3  << 0))
+
+	.equ	ESDCFG0_128MB, \
+		(0 << 21) + /* tXP */ \
+		(1 << 20) + /* tWTR */ \
+		(2 << 18) + /* tRP */ \
+		(1 << 16) + /* tMRD */ \
+		(0 << 15) + /* tWR */ \
+		(5 << 12) + /* tRAS */ \
+		(1 << 10) + /* tRRD */ \
+		(3 << 8) + /* tCAS */ \
+		(2 << 4) + /* tRCD */ \
+		(0x0F << 0) /* tRC */
+
+	.equ	ESDCTL0_128MB, \
+		(1 << 31)  +	/* enable */ \
+		(0 << 28)  +	/* mode */ \
+		(0 << 27)  +	/* supervisor protect */ \
+		(2 << 24)  +	/* 13 rows */ \
+		(2 << 20)  +	/* 10 cols */ \
+		(2 << 16)  +	/* 32 bit */ \
+		(3 << 13)  +	/* 7.81us (64ms/8192) */ \
+		(0 << 10)  +	/* power down timer */ \
+		(0 << 8)  +	/* full page */ \
+		(1 << 7)  +	/* burst length */ \
+		(0 << 0)	/* precharge timer */
+
+	.equ	ESDCFG0_256MB, \
+		(3 << 21)  + 	/* tXP */ \
+		(0 << 20)  + 	/* tWTR */ \
+		(2 << 18)  + 	/* tRP */ \
+		(1 << 16)  + 	/* tMRD */ \
+		(0 << 15)  + 	/* tWR */ \
+		(5 << 12)  + 	/* tRAS */ \
+		(1 << 10)  + 	/* tRRD */ \
+		(3 << 8)   + 	/* tCAS */ \
+		(2 << 4)   +	/* tRCD */ \
+		(7 << 0)	/* tRC */
+
+	.equ	ESDCTL0_256MB, \
+		(1 << 31)  + \
+		(0 << 28)  + \
+		(0 << 27)  + \
+		(3 << 24)  + /* 14 rows */ \
+		(2 << 20)  + /* 10 cols */ \
+		(2 << 16)  + \
+		(4 << 13)  + /* 3.91us (64ms/16384) */ \
+		(0 << 10)  + \
+		(0 << 8)   + \
+		(1 << 7)   + \
+		(0 << 0)
diff --git a/u-boot/board/davedenx/qong/qong.c b/u-boot/board/davedenx/qong/qong.c
new file mode 100644
index 0000000..8a81cfc
--- /dev/null
+++ b/u-boot/board/davedenx/qong/qong.c
@@ -0,0 +1,287 @@
+/*
+ *
+ * (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <fsl_pmic.h>
+#include <mxc_gpio.h>
+#include "qong_fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init (void)
+{
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+				PHYS_SDRAM_1_SIZE);
+	return 0;
+}
+
+static void qong_fpga_reset(void)
+{
+	mxc_gpio_set(QONG_FPGA_RST_PIN, 0);
+	udelay(30);
+	mxc_gpio_set(QONG_FPGA_RST_PIN, 1);
+
+	udelay(300);
+}
+
+int board_early_init_f (void)
+{
+#ifdef CONFIG_QONG_FPGA
+	/* CS1: FPGA/Network Controller/GPIO */
+	/* 16-bit, no DTACK */
+	__REG(CSCR_U(1)) = 0x00000A01;
+	__REG(CSCR_L(1)) = 0x20040501;
+	__REG(CSCR_A(1)) = 0x04020C00;
+
+	/* setup pins for FPGA */
+	mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO));
+	mx31_gpio_mux(IOMUX_MODE(0x7e, MUX_CTL_GPIO));
+	mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO));
+	mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO));
+	mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO));
+
+	/* FPGA reset  Pin */
+	/* rstn = 0 */
+	mxc_gpio_set(QONG_FPGA_RST_PIN, 0);
+	mxc_gpio_direction(QONG_FPGA_RST_PIN, MXC_GPIO_DIRECTION_OUT);
+
+	/* set interrupt pin as input */
+	mxc_gpio_direction(QONG_FPGA_IRQ_PIN, MXC_GPIO_DIRECTION_IN);
+
+	/* FPGA JTAG Interface */
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS6, MUX_CTL_GPIO));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK6, MUX_CTL_GPIO));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CAPTURE, MUX_CTL_GPIO));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_COMPARE, MUX_CTL_GPIO));
+	mxc_gpio_direction(QONG_FPGA_TCK_PIN, MXC_GPIO_DIRECTION_OUT);
+	mxc_gpio_direction(QONG_FPGA_TMS_PIN, MXC_GPIO_DIRECTION_OUT);
+	mxc_gpio_direction(QONG_FPGA_TDI_PIN, MXC_GPIO_DIRECTION_OUT);
+	mxc_gpio_direction(QONG_FPGA_TDO_PIN, MXC_GPIO_DIRECTION_IN);
+#endif
+
+	/* setup pins for UART1 */
+	mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
+	mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
+	mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
+	mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
+
+	/* setup pins for SPI (pmic) */
+	mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
+	mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
+	mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
+	mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
+	mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
+
+	/* Setup pins for USB2 Host */
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_CLK, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DIR, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_NXT, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD3, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD3, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK3, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS3, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD6, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD6, MUX_CTL_FUNC));
+
+#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
+			PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
+
+	mx31_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
+	mx31_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
+	mx31_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
+	mx31_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
+	mx31_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
+	mx31_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
+	mx31_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG);	/* USBH2_DATA2 */
+	mx31_set_pad(MX31_PIN_STXD6, H2_PAD_CFG);	/* USBH2_DATA3 */
+	mx31_set_pad(MX31_PIN_SFS3, H2_PAD_CFG);	/* USBH2_DATA4 */
+	mx31_set_pad(MX31_PIN_SCK3, H2_PAD_CFG);	/* USBH2_DATA5 */
+	mx31_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG);	/* USBH2_DATA6 */
+	mx31_set_pad(MX31_PIN_STXD3, H2_PAD_CFG);	/* USBH2_DATA7 */
+
+	writel(readl((IOMUXC_BASE + 0x8)) | (1 << 11), IOMUXC_BASE + 0x8);
+
+	return 0;
+
+}
+
+int board_init (void)
+{
+	/* Chip selects */
+	/* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */
+	/* Assumptions: HCLK = 133 MHz, tACC = 130ns */
+	__REG(CSCR_U(0)) = ((0 << 31)	| /* SP */
+						(0 << 30)	| /* WP */
+						(0 << 28)	| /* BCD */
+						(0 << 24)	| /* BCS */
+						(0 << 22)	| /* PSZ */
+						(0 << 21)	| /* PME */
+						(0 << 20)	| /* SYNC */
+						(0 << 16)	| /* DOL */
+						(3 << 14)	| /* CNC */
+						(21 << 8)	| /* WSC */
+						(0 << 7)	| /* EW */
+						(0 << 4)	| /* WWS */
+						(6 << 0)	  /* EDC */
+					   );
+
+	__REG(CSCR_L(0)) = ((2 << 28)	| /* OEA */
+						(1 << 24)	| /* OEN */
+						(3 << 20)	| /* EBWA */
+						(3 << 16)	| /* EBWN */
+						(1 << 12)	| /* CSA */
+						(1 << 11)	| /* EBC */
+						(5 << 8)	| /* DSZ */
+						(1 << 4)	| /* CSN */
+						(0 << 3)	| /* PSR */
+						(0 << 2)	| /* CRE */
+						(0 << 1)	| /* WRAP */
+						(1 << 0)	  /* CSEN */
+					   );
+
+	__REG(CSCR_A(0)) = ((2 << 28)	| /* EBRA */
+						(1 << 24)	| /* EBRN */
+						(2 << 20)	| /* RWA */
+						(2 << 16)	| /* RWN */
+						(0 << 15)	| /* MUM */
+						(0 << 13)	| /* LAH */
+						(2 << 10)	| /* LBN */
+						(0 << 8)	| /* LBA */
+						(0 << 6)	| /* DWW */
+						(0 << 4)	| /* DCT */
+						(0 << 3)	| /* WWU */
+						(0 << 2)	| /* AGE */
+						(0 << 1)	| /* CNC2 */
+						(0 << 0)	  /* FCE */
+					   );
+
+	/* board id for linux */
+	gd->bd->bi_arch_number = MACH_TYPE_QONG;
+	gd->bd->bi_boot_params = (0x80000100);	/* adress of boot parameters */
+
+	qong_fpga_init();
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	u32 val;
+
+	/* Enable RTC battery */
+	val = pmic_reg_read(REG_POWER_CTL0);
+	pmic_reg_write(REG_POWER_CTL0, val | COINCHEN);
+	pmic_reg_write(REG_INT_STATUS1, RTCRSTI);
+
+	return 0;
+}
+
+int checkboard (void)
+{
+	printf("Board: DAVE/DENX Qong\n");
+	return 0;
+}
+
+int misc_init_r (void)
+{
+#ifdef CONFIG_QONG_FPGA
+	u32 tmp;
+
+	tmp = *(volatile u32*)QONG_FPGA_CTRL_VERSION;
+	printf("FPGA:  ");
+	printf("version register = %u.%u.%u\n",
+		(tmp & 0xF000) >> 12, (tmp & 0x0F00) >> 8, tmp & 0x00FF);
+#endif
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_DNET)
+	return dnet_eth_initialize(0, (void *)CONFIG_DNET_BASE, -1);
+#else
+	return 0;
+#endif
+}
+
+#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT)
+static void board_nand_setup(void)
+{
+
+	/* CS3: NAND 8-bit */
+	__REG(CSCR_U(3)) = 0x00004f00;
+	__REG(CSCR_L(3)) = 0x20013b31;
+	__REG(CSCR_A(3)) = 0x00020800;
+	__REG(IOMUXC_GPR) |= 1 << 13;
+
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_RB, MUX_CTL_IN_GPIO));
+
+	/* Make sure to reset the fpga else you cannot access NAND */
+	qong_fpga_reset();
+
+	/* Enable NAND flash */
+	mxc_gpio_set(15, 1);
+	mxc_gpio_set(14, 1);
+	mxc_gpio_direction(15, MXC_GPIO_DIRECTION_OUT);
+	mxc_gpio_direction(16, MXC_GPIO_DIRECTION_IN);
+	mxc_gpio_direction(14, MXC_GPIO_DIRECTION_IN);
+	mxc_gpio_set(15, 0);
+
+}
+
+int qong_nand_rdy(void *chip)
+{
+	udelay(1);
+	return mxc_gpio_get(16);
+}
+
+void qong_nand_select_chip(struct mtd_info *mtd, int chip)
+{
+	if (chip >= 0)
+		mxc_gpio_set(15, 0);
+	else
+		mxc_gpio_set(15, 1);
+
+}
+
+void qong_nand_plat_init(void *chip)
+{
+	struct nand_chip *nand = (struct nand_chip *)chip;
+	nand->chip_delay = 20;
+	nand->select_chip = qong_nand_select_chip;
+	nand->options &= ~NAND_BUSWIDTH_16;
+	board_nand_setup();
+}
+
+#endif
diff --git a/u-boot/board/davedenx/qong/qong_fpga.h b/u-boot/board/davedenx/qong/qong_fpga.h
new file mode 100644
index 0000000..4e79ac2
--- /dev/null
+++ b/u-boot/board/davedenx/qong/qong_fpga.h
@@ -0,0 +1,39 @@
+/*
+ *
+ * (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef QONG_FPGA_H
+#define QONG_FPGA_H
+
+#define QONG_FPGA_CTRL_BASE		CONFIG_FPGA_BASE
+#define QONG_FPGA_CTRL_VERSION		(QONG_FPGA_CTRL_BASE + 0x00000000)
+#define QONG_FPGA_PERIPH_SIZE		(1 << 24)
+
+#define	QONG_FPGA_TCK_PIN		26
+#define	QONG_FPGA_TMS_PIN		25
+#define	QONG_FPGA_TDI_PIN		8
+#define	QONG_FPGA_TDO_PIN		7
+#define	QONG_FPGA_RST_PIN		48
+#define	QONG_FPGA_IRQ_PIN		40
+
+int qong_fpga_init(void);
+#endif /* QONG_FPGA_H */