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author | H. Nikolaus Schaller <hns@goldelico.com> | 2012-03-26 20:55:28 +0200 |
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committer | H. Nikolaus Schaller <hns@goldelico.com> | 2012-03-26 20:55:28 +0200 |
commit | 92988a21ad4c4c9504295ccb580c9f806134471b (patch) | |
tree | 5effc9f14170112450de05c67dafbe8d5034d595 /u-boot/board/esd/cpci2dp | |
parent | ca2b506783b676c95762c54ea24dcfdaae1947c9 (diff) | |
download | bootable_bootloader_goldelico_gta04-92988a21ad4c4c9504295ccb580c9f806134471b.zip bootable_bootloader_goldelico_gta04-92988a21ad4c4c9504295ccb580c9f806134471b.tar.gz bootable_bootloader_goldelico_gta04-92988a21ad4c4c9504295ccb580c9f806134471b.tar.bz2 |
added boot script files to repository
Diffstat (limited to 'u-boot/board/esd/cpci2dp')
-rw-r--r-- | u-boot/board/esd/cpci2dp/Makefile | 53 | ||||
-rw-r--r-- | u-boot/board/esd/cpci2dp/cpci2dp.c | 188 | ||||
-rw-r--r-- | u-boot/board/esd/cpci2dp/flash.c | 84 |
3 files changed, 325 insertions, 0 deletions
diff --git a/u-boot/board/esd/cpci2dp/Makefile b/u-boot/board/esd/cpci2dp/Makefile new file mode 100644 index 0000000..be65097 --- /dev/null +++ b/u-boot/board/esd/cpci2dp/Makefile @@ -0,0 +1,53 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif + +LIB = $(obj)lib$(BOARD).o + +COBJS = $(BOARD).o flash.o ../common/misc.o ../common/cmd_loadpci.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/u-boot/board/esd/cpci2dp/cpci2dp.c b/u-boot/board/esd/cpci2dp/cpci2dp.c new file mode 100644 index 0000000..ecfcf59 --- /dev/null +++ b/u-boot/board/esd/cpci2dp/cpci2dp.c @@ -0,0 +1,188 @@ +/* + * (C) Copyright 2005 + * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <command.h> +#include <malloc.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f (void) +{ + unsigned long CPC0_CR0Reg; + + /* + * Setup GPIO pins + */ + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | + ((CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED | + CONFIG_SYS_SELF_RST | CONFIG_SYS_INTA_FAKE) << 5)); + + /* set output pins to high */ + out_be32((void *)GPIO0_OR, CONFIG_SYS_EEPROM_WP); + /* setup for output (LED=off) */ + out_be32((void *)GPIO0_TCR, CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED); + + /* + * IRQ 0-15 405GP internally generated; active high; level sensitive + * IRQ 16 405GP internally generated; active low; level sensitive + * IRQ 17-24 RESERVED + * IRQ 25 (EXT IRQ 0) PB0; active low; level sensitive + * IRQ 26 (EXT IRQ 1) PB1; active low; level sensitive + * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive + * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive + * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive + * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive + * IRQ 31 (EXT IRQ 6) unused + */ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr(UIC0ER, 0x00000000); /* disable all ints */ + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/ + mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */ + + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ + + return 0; +} + +int misc_init_r (void) +{ + unsigned long CPC0_CR0Reg; + + /* adjust flash start and offset */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + + /* + * Select cts (and not dsr) on uart1 + */ + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000); + + return (0); +} + + +/* + * Check Board Identity: + */ +int checkboard (void) +{ + char str[64]; + int i = getenv_f("serial#", str, sizeof(str)); + + puts ("Board: "); + + if (i == -1) { + puts ("### No HW ID - assuming CPCI2DP"); + } else { + puts(str); + } + + printf(" (Ver 1.0)"); + + putc ('\n'); + + return 0; +} + +#if defined(CONFIG_SYS_EEPROM_WREN) +/* Input: <dev_addr> I2C address of EEPROM device to enable. + * <state> -1: deliver current state + * 0: disable write + * 1: enable write + * Returns: -1: wrong device address + * 0: dis-/en- able done + * 0/1: current state if <state> was -1. + */ +int eeprom_write_enable (unsigned dev_addr, int state) { + if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { + return -1; + } else { + switch (state) { + case 1: + /* Enable write access, clear bit GPIO_SINT2. */ + out_be32((void *)GPIO0_OR, + in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP); + state = 0; + break; + case 0: + /* Disable write access, set bit GPIO_SINT2. */ + out_be32((void *)GPIO0_OR, + in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); + state = 0; + break; + default: + /* Read current status back. */ + state = (0 == (in_be32((void *)GPIO0_OR) & + CONFIG_SYS_EEPROM_WP)); + break; + } + } + return state; +} +#endif + +#if defined(CONFIG_SYS_EEPROM_WREN) +int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int query = argc == 1; + int state = 0; + + if (query) { + /* Query write access state. */ + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1); + if (state < 0) { + puts ("Query of write access state failed.\n"); + } else { + printf ("Write access for device 0x%0x is %sabled.\n", + CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); + state = 0; + } + } else { + if ('0' == argv[1][0]) { + /* Disable write access. */ + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0); + } else { + /* Enable write access. */ + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1); + } + if (state < 0) { + puts ("Setup of write access state failed.\n"); + } + } + + return state; +} + +U_BOOT_CMD( + eepwren, 2, 0, do_eep_wren, + "Enable / disable / query EEPROM write access", + "" +); +#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ diff --git a/u-boot/board/esd/cpci2dp/flash.c b/u-boot/board/esd/cpci2dp/flash.c new file mode 100644 index 0000000..b210281 --- /dev/null +++ b/u-boot/board/esd/cpci2dp/flash.c @@ -0,0 +1,84 @@ +/* + * (C) Copyright 2001 + * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/ppc4xx.h> +#include <asm/processor.h> + +/* + * include common flash code (for esd boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static void flash_get_offsets (ulong base, flash_info_t *info); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0; + int i; + uint pbcr; + unsigned long base_b0; + + /* Init: no FLASHes known */ + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Static FLASH Bank configuration here - FIXME XXX */ + + size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0<<20); + } + + /* Setup offsets */ + flash_get_offsets (-size_b0, &flash_info[0]); + + /* Re-do sizing to get full correct info */ + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); + base_b0 = -size_b0; + pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17); + mtdcr(EBC0_CFGDATA, pbcr); + /* printf("PB1CR = %x\n", pbcr); */ + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + -monitor_flash_len, + 0xffffffff, + &flash_info[0]); + + flash_info[0].size = size_b0; + + return (size_b0); +} |