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-rw-r--r--x-loader/board/omap1710h3/Makefile47
-rw-r--r--x-loader/board/omap1710h3/config.mk26
-rw-r--r--x-loader/board/omap1710h3/omap1710h3.c89
-rw-r--r--x-loader/board/omap1710h3/platform.S410
-rw-r--r--x-loader/board/omap1710h3/x-load.lds49
-rw-r--r--x-loader/cpu/arm926ejs/Makefile43
-rw-r--r--x-loader/cpu/arm926ejs/config.mk32
-rw-r--r--x-loader/cpu/arm926ejs/cpu.c126
-rw-r--r--x-loader/cpu/arm926ejs/start.S239
-rw-r--r--x-loader/drivers/k9f5616.c229
-rw-r--r--x-loader/include/configs/omap1510.h698
-rw-r--r--x-loader/include/configs/omap1710h3.h128
12 files changed, 0 insertions, 2116 deletions
diff --git a/x-loader/board/omap1710h3/Makefile b/x-loader/board/omap1710h3/Makefile
deleted file mode 100644
index 94f5821..0000000
--- a/x-loader/board/omap1710h3/Makefile
+++ /dev/null
@@ -1,47 +0,0 @@
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = lib$(BOARD).a
-
-OBJS := omap1710h3.o
-SOBJS := platform.o
-
-$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
-
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-
--include .depend
-
-#########################################################################
diff --git a/x-loader/board/omap1710h3/config.mk b/x-loader/board/omap1710h3/config.mk
deleted file mode 100644
index d9e3c76..0000000
--- a/x-loader/board/omap1710h3/config.mk
+++ /dev/null
@@ -1,26 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
-# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
-#
-# (C) Copyright 2004
-# Texas Instruments, <www.ti.com>
-# Kshitij Gupta <Kshitij@ti.com>
-#
-# TI H3 board with OMAP1710 (ARM925EJS) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# Innovator has 1 bank of 256 MB SDRAM
-# Physical Address:
-# 1000'0000 to 2000'0000
-#
-#
-# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
-# (mem base + reserved)
-#
-# we load ourself to 1108'0000
-#
-#
-
-PLATFORM_LDFLAGS += -no-warn-mismatch
-TEXT_BASE = 0x11080000
diff --git a/x-loader/board/omap1710h3/omap1710h3.c b/x-loader/board/omap1710h3/omap1710h3.c
deleted file mode 100644
index 245cfe2..0000000
--- a/x-loader/board/omap1710h3/omap1710h3.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Jian Zhang <jzhang@ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#if defined(CONFIG_OMAP1710)
-#include <./configs/omap1510.h>
-#endif
-
-#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
-
-int board_init (void)
-{
-#ifdef CFG_PRINTF
-
- /* setup for UART1 */
- *(volatile unsigned int *) ((unsigned int)FUNC_MUX_CTRL_0) &= ~(0x02000000); /* bit 25 */
- /* bit 29 for UART1 */
- *(volatile unsigned int *) ((unsigned int)MOD_CONF_CTRL_0) &= ~(0x00002000);
-
- /* Enable the power for UART1 */
-#define UART1_48MHZ_ENABLE ((unsigned short)0x0200)
-#define SW_CLOCK_REQUEST 0xFFFE0834
- *((volatile unsigned short *)SW_CLOCK_REQUEST) |= UART1_48MHZ_ENABLE;
-
-#endif
-
- *(volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0) = COMP_MODE_ENABLE;
- return 0;
-}
-
-#define GPIO1_DIRECTION 0xFFFBE434
-#define FUNC_MUX_CTRL_F 0xFFFE1094
-#define PU_PD_SEL_4 0xFFFE10C4
-/*
- * On H3 board, Nand R/B is tied to GPIO_10
- * We setup this GPIO pin
- */
-int nand_init (void)
-{
-
- /* GPIO_10 for input. it is in GPIO1 module */
- *(volatile unsigned int *) ((unsigned int)GPIO1_DIRECTION) |= 0x0400;
-
- /* GPIO10 Func_MUX_CTRL reg bit 29:27, Configure V2 to mode1 as GPIO */
- *(volatile unsigned int *) ((unsigned int)FUNC_MUX_CTRL_F) &= 0xC7FFFFFF;
- *(volatile unsigned int *) ((unsigned int)FUNC_MUX_CTRL_F) |= 0x08000000;
-
- /* GPIO10 pullup/down register, Enable pullup on GPIO10 */
- *(volatile unsigned int *) ((unsigned int)PU_PD_SEL_4) |= 0x08;
-
- if (nand_chip()){
- printf("Unsupported Chip!\n");
- return 1;
- }
- return 0;
-}
-
-/* optionally do something like blinking LED */
-void board_hang (void)
-{}
-
diff --git a/x-loader/board/omap1710h3/platform.S b/x-loader/board/omap1710h3/platform.S
deleted file mode 100644
index ef64e3e..0000000
--- a/x-loader/board/omap1710h3/platform.S
+++ /dev/null
@@ -1,410 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2004
- * Texas Instruments, <www.ti.com>
- * Jian Zhang <jzhang@ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#if defined(CONFIG_OMAP1710)
-#include <./configs/omap1510.h>
-#endif
-
-
-_TEXT_BASE:
- .word TEXT_BASE /* sdram load addr from config.mk */
-
-.globl platformsetup
-platformsetup:
-
-
- /*------------------------------------------------------*
- * Set up ARM CLM registers (IDLECT1) *
- *------------------------------------------------------*/
- ldr r0, REG_ARM_IDLECT1
- ldr r1, VAL_ARM_IDLECT1
- str r1, [r0]
-
- /*------------------------------------------------------*
- * Set up ARM CLM registers (IDLECT2) *
- *------------------------------------------------------*/
- ldr r0, REG_ARM_IDLECT2
- ldr r1, VAL_ARM_IDLECT2
- str r1, [r0]
-
- /*------------------------------------------------------*
- * Set up ARM CLM registers (IDLECT3) *
- *------------------------------------------------------*/
- ldr r0, REG_ARM_IDLECT3
- ldr r1, VAL_ARM_IDLECT3
- str r1, [r0]
-
-
- mov r1, #0x05 /* PER_EN bit */
- ldr r0, REG_ARM_RSTCT2
- strh r1, [r0] /* CLKM; Peripheral reset. */
-
- /* Set CLKM to Sync-Scalable */
- /* I supposedly need to enable the dsp clock before switching */
- ldr r1, VAL_ARM_SYSST
- ldr r0, REG_ARM_SYSST
- strh r1, [r0]
- mov r0, #0x400
-1:
- subs r0, r0, #0x1 /* wait for any bubbles to finish */
- bne 1b
- ldr r1, VAL_ARM_CKCTL
- ldr r0, REG_ARM_CKCTL
- strh r1, [r0]
-
- /* a few nops to let settle */
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
-
- /* setup DPLL 1 */
- /* Ramp up the clock to 96Mhz */
- ldr r1, VAL_DPLL1_CTL
- ldr r0, REG_DPLL1_CTL
- strh r1, [r0]
- ands r1, r1, #0x10 /* Check if PLL is enabled. */
- beq lock_end /* Do not look for lock if BYPASS selected */
-2:
- ldrh r1, [r0]
- ands r1, r1, #0x01 /* Check the LOCK bit.*/
- beq 2b /* loop until bit goes hi. */
-lock_end:
-
-
- /*------------------------------------------------------*
- * Turn off the watchdog during init... *
- *------------------------------------------------------*/
- ldr r0, REG_WATCHDOG
- ldr r1, WATCHDOG_VAL1
- str r1, [r0]
- ldr r1, WATCHDOG_VAL2
- str r1, [r0]
- ldr r0, REG_WSPRDOG
- ldr r1, WSPRDOG_VAL1
- str r1, [r0]
- ldr r0, REG_WWPSDOG
-
-watch1Wait:
- ldr r1, [r0]
- tst r1, #0x10
- bne watch1Wait
-
- ldr r0, REG_WSPRDOG
- ldr r1, WSPRDOG_VAL2
- str r1, [r0]
- ldr r0, REG_WWPSDOG
-watch2Wait:
- ldr r1, [r0]
- tst r1, #0x10
- bne watch2Wait
-
-
- /* Set memory timings corresponding to the new clock speed */
-
- /*
- * Delay for SDRAM initialization.
- */
- mov r3, #0x1800 /* value should be checked */
-3:
- subs r3, r3, #0x1 /* Decrement count */
- bne 3b
-
-
- /*
- * Set SDRAM control values. Disable refresh before MRS command.
- */
-
- /* mobile ddr operation */
- ldr r0, REG_SDRAM_OPERATION
- mov r2, #07
- str r2, [r0]
-
- /* config register */
- ldr r0, REG_SDRAM_CONFIG
- ldr r1, SDRAM_CONFIG_VAL
- str r1, [r0]
-
- /* manual command register */
- ldr r0, REG_SDRAM_MANUAL_CMD
- /* issue set cke high */
- mov r1, #CMD_SDRAM_CKE_SET_HIGH
- str r1, [r0]
- /* issue nop */
- mov r1, #CMD_SDRAM_NOP
- str r1, [r0]
-
- mov r2, #0x0100
-waitMDDR1:
- subs r2, r2, #1
- bne waitMDDR1 /* delay loop */
-
- /* issue precharge */
- mov r1, #CMD_SDRAM_PRECHARGE
- str r1, [r0]
-
-
- /* issue autorefresh x 2 */
- mov r1, #CMD_SDRAM_AUTOREFRESH
- str r1, [r0]
- str r1, [r0]
-
- /* mrs register ddr mobile */
- ldr r0, REG_SDRAM_MRS
- mov r1, #0x33
- str r1, [r0]
-
- /* emrs1 low-power register */
- ldr r0, REG_SDRAM_EMRS1
- /* self refresh on all banks */
- mov r1, #0
- str r1, [r0]
-
- ldr r0, REG_DLL_URD_CONTROL
- ldr r1, DLL_URD_CONTROL_VAL
- str r1, [r0]
-
- ldr r0, REG_DLL_LRD_CONTROL
- ldr r1, DLL_LRD_CONTROL_VAL
- str r1, [r0]
-
- ldr r0, REG_DLL_WRT_CONTROL
- ldr r1, DLL_WRT_CONTROL_VAL
- str r1, [r0]
-
- /* delay loop */
- mov r2, #0x0100
-waitMDDR2:
- subs r2, r2, #1
- bne waitMDDR2
-
- /*
- * Delay for SDRAM initialization.
- */
- mov r3, #0x1800
-4:
- subs r3, r3, #1 /* Decrement count. */
- bne 4b
- b common_tc
-
-skip_sdram:
-
- ldr r0, REG_SDRAM_CONFIG
- ldr r1, SDRAM_CONFIG_VAL
- str r1, [r0]
-
- /* Enable EMIFF TC Doubler in OMAP1710 */
- ldr r0, REG_EMIFF_DOUBLER
- mov r0, #0x1;
-
-common_tc:
- /* slow interface */
- ldr r1, VAL_TC_EMIFS_CONFIG
- ldr r0, REG_TC_EMIFS_CONFIG
- str r1, [r0]
-
-#ifdef CFG_BOOT_CS0
- /* Chip Select 3 for NAND*/
- ldr r1, VAL_TC_EMIFS_CS3_CONFIG
- ldr r0, REG_TC_EMIFS_CS3_CONFIG
- str r1, [r0]
-#else
- /* Chip Select 2 for NAND*/
- ldr r1, VAL_TC_EMIFS_CS2_CONFIG
- ldr r0, REG_TC_EMIFS_CS2_CONFIG
- str r1, [r0]
-#endif
-
- /* Start MPU Timer 1 */
- ldr r0, REG_MPU_LOAD_TIMER
- ldr r1, VAL_MPU_LOAD_TIMER
- str r1, [r0]
-
- ldr r0, REG_MPU_CNTL_TIMER
- ldr r1, VAL_MPU_CNTL_TIMER
- str r1, [r0]
-
- /* back to arch calling code */
- mov pc, lr
-
- /* the literal pools origin */
- .ltorg
-
-
-REG_TC_EMIFS_CONFIG: /* 32 bits */
- .word 0xfffecc0c
-#ifdef CFG_BOOT_CS0
-REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
- .word 0xfffecc1c
-#else
-REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
- .word 0xfffecc18
-#endif
-
-/* MPU clock/reset/power mode control registers */
-REG_ARM_CKCTL: /* 16 bits */
- .word 0xfffece00
-
-REG_ARM_IDLECT3: /* 16 bits */
- .word 0xfffece24
-REG_ARM_IDLECT2: /* 16 bits */
- .word 0xfffece08
-REG_ARM_IDLECT1: /* 16 bits */
- .word 0xfffece04
-
-REG_ARM_RSTCT2: /* 16 bits */
- .word 0xfffece14
-REG_ARM_SYSST: /* 16 bits */
- .word 0xfffece18
-/* DPLL control registers */
-REG_DPLL1_CTL: /* 16 bits */
- .word 0xfffecf00
-
-/* Watch Dog register */
-/* secure watchdog stop */
-REG_WSPRDOG:
- .word 0xfffeb048
-/* watchdog write pending */
-REG_WWPSDOG:
- .word 0xfffeb034
-
-WSPRDOG_VAL1:
- .word 0x0000aaaa
-WSPRDOG_VAL2:
- .word 0x00005555
-
-/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
- counter @8192 rows, 10 ns, 8 burst */
-REG_SDRAM_CONFIG:
- .word 0xfffecc20
-
-/* Operation register */
-REG_SDRAM_OPERATION:
- .word 0xfffecc80
-
-REG_EMIFF_DOUBLER:
- .word 0xfffecc60
-
-/* Manual command register */
-REG_SDRAM_MANUAL_CMD:
- .word 0xfffecc84
-
-/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
-REG_SDRAM_MRS:
- .word 0xfffecc70
-
-/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
-REG_SDRAM_EMRS1:
- .word 0xfffecc78
-
-/* WRT DLL register */
-REG_DLL_WRT_CONTROL:
- .word 0xfffecc64
-DLL_WRT_CONTROL_VAL:
- .word 0x03500002
-
-/* URD DLL register */
-REG_DLL_URD_CONTROL:
- .word 0xfffeccc0
-DLL_URD_CONTROL_VAL:
- .word 0x00000006
-
-/* LRD DLL register */
-REG_DLL_LRD_CONTROL:
- .word 0xfffecccc
-
-REG_WATCHDOG:
- .word 0xfffec808
-
-REG_MPU_LOAD_TIMER:
- .word 0xfffec600
-REG_MPU_CNTL_TIMER:
- .word 0xfffec500
-
-/* 96 MHz Samsung Mobile DDR */
-SDRAM_CONFIG_VAL:
- .word 0x0c028af4
-
-DLL_LRD_CONTROL_VAL:
- .word 0x00000006
-
-VAL_ARM_CKCTL:
- .word 0x350e
-VAL_ARM_SYSST:
- .word 0x1001
-
-VAL_DPLL1_CTL:
- .word 0x2810
-
-#ifdef CFG_BOOT_CS0
-VAL_TC_EMIFS_CONFIG:
- .word 0x00000010
-VAL_TC_EMIFS_CS3_CONFIG:
- .word 0xff80fff3
-#else
-VAL_TC_EMIFS_CONFIG:
- .word 0x00000012 /*swap CS0/CS3 addressing */
-VAL_TC_EMIFS_CS2_CONFIG:
- .word 0xff80fff3
-#endif
-
-
-VAL_TC_EMIFF_SDRAM_CONFIG:
- .word 0x010290fc
-VAL_TC_EMIFF_MRS:
- .word 0x00000027
-
-VAL_ARM_IDLECT1:
- .word 0x000014c6
-
-VAL_ARM_IDLECT2:
- .word 0x000009ff
-VAL_ARM_IDLECT3:
- .word 0x0000003f
-
-WATCHDOG_VAL1:
- .word 0x000000f5
-WATCHDOG_VAL2:
- .word 0x000000a0
-
-VAL_MPU_LOAD_TIMER:
- .word 0xffffffff
-VAL_MPU_CNTL_TIMER:
- .word 0xffffffa1
-
-/* command values */
-.equ CMD_SDRAM_NOP, 0x00000000
-.equ CMD_SDRAM_PRECHARGE, 0x00000001
-.equ CMD_SDRAM_AUTOREFRESH, 0x00000002
-.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007
diff --git a/x-loader/board/omap1710h3/x-load.lds b/x-loader/board/omap1710h3/x-load.lds
deleted file mode 100644
index 7b84eea..0000000
--- a/x-loader/board/omap1710h3/x-load.lds
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * (C) Copyright 2004 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
- . = ALIGN(4);
- .text :
- {
- cpu/arm926ejs/start.o (.text)
- *(.text)
- }
- . = ALIGN(4);
- .rodata : { *(.rodata) }
- . = ALIGN(4);
- .data : { *(.data) }
- . = ALIGN(4);
- .got : { *(.got) }
-
- . = ALIGN(4);
- __bss_start = .;
- .bss : { *(.bss) }
- _end = .;
-}
diff --git a/x-loader/cpu/arm926ejs/Makefile b/x-loader/cpu/arm926ejs/Makefile
deleted file mode 100644
index 229b7e7..0000000
--- a/x-loader/cpu/arm926ejs/Makefile
+++ /dev/null
@@ -1,43 +0,0 @@
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = lib$(CPU).a
-
-START = start.o
-OBJS = cpu.o
-
-all: .depend $(START) $(LIB)
-
-$(LIB): $(OBJS)
- $(AR) crv $@ $(OBJS)
-
-#########################################################################
-
-.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
-
-sinclude .depend
-
-#########################################################################
diff --git a/x-loader/cpu/arm926ejs/config.mk b/x-loader/cpu/arm926ejs/config.mk
deleted file mode 100644
index f9adb10..0000000
--- a/x-loader/cpu/arm926ejs/config.mk
+++ /dev/null
@@ -1,32 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8
-
-PLATFORM_CPPFLAGS += -march=armv5
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
-PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-#
diff --git a/x-loader/cpu/arm926ejs/cpu.c b/x-loader/cpu/arm926ejs/cpu.c
deleted file mode 100644
index 972fa8a..0000000
--- a/x-loader/cpu/arm926ejs/cpu.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments <www.ti.com>
- * Jian Zhang <jzhang@ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#define TIMER_LOAD_VAL 0xffffffff
-
-/* macro to read the 32 bit timer */
-#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8))
-
-static ulong timestamp;
-static ulong lastdec;
-
-static void reset_timer_masked (void);
-
-/* nothing really to do with cpu, just starts up a counter. */
-int cpu_init (void)
-{
- int32_t val;
-
- /* Start the decrementer ticking down from 0xffffffff */
- *((int32_t *) (CFG_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
- val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CFG_PVT << MPUTIM_PTV_BIT);
- *((int32_t *) (CFG_TIMERBASE + CNTL_TIMER)) = val;
-
- /* init the timestamp and lastdec value */
- reset_timer_masked();
-
- return (0);
-}
-
-static void reset_timer_masked (void)
-{
- /* reset time */
- lastdec = READ_TIMER; /* capure current decrementer value time */
- timestamp = 0; /* start "advancing" time stamp from 0 */
-}
-
-#ifdef CFG_UDELAY
-
-static ulong get_timer_masked (void);
-static ulong get_timer (ulong base);
-
-/* delay x useconds AND perserve advance timstamp value */
-void udelay (unsigned long usec)
-{
- ulong tmo, tmp;
-
- if(usec >= 1000){ /* if "big" number, spread normalization to seconds */
- tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
- tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
- tmo /= 1000; /* finish normalize. */
- }else{ /* else small number, don't kill it prior to HZ multiply */
- tmo = usec * CFG_HZ;
- tmo /= (1000*1000);
- }
-
- tmp = get_timer (0); /* get current timestamp */
- if( (tmo + tmp) < tmp ) /* if setting this fordward will roll time stamp */
- reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastdec value */
- else
- tmo += tmp; /* else, set advancing stamp wake up time */
-
- while (get_timer_masked () < tmo)/* loop till event */
- /*NOP*/;
-}
-
-static ulong get_timer_masked (void)
-{
- ulong now = READ_TIMER; /* current tick value */
-
- if (lastdec >= now) { /* normal mode (non roll) */
- /* normal mode */
- timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */
- } else { /* we have overflow of the count down timer */
- /* nts = ts + ld + (TLV - now)
- * ts=old stamp, ld=time that passed before passing through -1
- * (TLV-now) amount of time after passing though -1
- * nts = new "advancing time stamp"...it could also roll and cause problems.
- */
- timestamp += lastdec + TIMER_LOAD_VAL - now;
- }
- lastdec = now;
-
- return timestamp;
-}
-
-static ulong get_timer (ulong base)
-{
- return get_timer_masked () - base;
-}
-
-#endif /* CFG_UDELAY */
-
diff --git a/x-loader/cpu/arm926ejs/start.S b/x-loader/cpu/arm926ejs/start.S
deleted file mode 100644
index 2211dae..0000000
--- a/x-loader/cpu/arm926ejs/start.S
+++ /dev/null
@@ -1,239 +0,0 @@
-/*
- * armboot - Startup Code for ARM926EJS CPU-core
- *
- * Copyright (c) 2003 Texas Instruments
- *
- * ----- Adapted for OMAP1610 from ARM925t code ------
- *
- * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
- * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
- * Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
- * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
- * Copyright (c) 2003 Kshitij <kshitij@ti.com>
- * Copyright (c) 2004 Jian Zhang <jzhang@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <config.h>
-#if defined(CONFIG_OMAP1610)
-#include <./configs/omap1510.h>
-#endif
-
-/*
- *************************************************************************
- *
- * Jump vector table as in table 3.1 in [1]
- *
- *************************************************************************
- */
-
-
-.globl _start
-_start:
- b reset
- ldr pc, _hang
- ldr pc, _hang
- ldr pc, _hang
- ldr pc, _hang
- ldr pc, _hang
- ldr pc, _hang
- ldr pc, _hang
-
-_hang:
- .word do_hang
-
- .balignl 16,0xdeadbeef
-
-
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * setup Memory and board specific bits prior to relocation.
- * relocate armboot to ram
- * setup stack
- *
- *************************************************************************
- */
-
-_TEXT_BASE:
- .word TEXT_BASE
-
-.globl _armboot_start
-_armboot_start:
- .word _start
-
-/*
- * These are defined in the board-specific linker script.
- */
-.globl _bss_start
-_bss_start:
- .word __bss_start
-
-.globl _bss_end
-_bss_end:
- .word _end
-
-
-/*
- * the actual reset code
- */
-
-reset:
- /*
- * set the cpu to SVC32 mode
- */
- mrs r0,cpsr
- bic r0,r0,#0x1f
- orr r0,r0,#0xd3
- msr cpsr,r0
-
- /*
- * turn off the watchdog, unlock/diable sequence
- */
- mov r1, #0xF5
- ldr r0, =WDTIM_MODE
- strh r1, [r0]
- mov r1, #0xA0
- strh r1, [r0]
-
-
- /*
- * mask all IRQs by setting all bits in the INTMR - default
- */
-
- mov r1, #0xffffffff
- ldr r0, =REG_IHL1_MIR
- str r1, [r0]
- ldr r0, =REG_IHL2_MIR
- str r1, [r0]
-
- /*
- * we do sys-critical inits at reboot,
- */
- bl cpu_init_crit
-
- /*
- * relocate exception vectors to SRAM where ROM code expects
- */
-#ifdef CFG_BOOT_CS0
-
- adr r0, _start /* r0 <- current position of code */
- add r0, r0, #4 /* skip reset vector */
- mov r2, #36 /* r2 <- size of data (8+1 words) */
- add r2, r0, r2 /* r2 <- source end address */
- mov r1, #0x20000000
-next:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- ble next
-
-#endif
-
-relocate: /* relocate X-Loader to RAM */
- adr r0, _start /* r0 <- current position of code */
- ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
- cmp r0, r1 /* don't reloc during debug */
- /*beq stack_setup*/
-
- ldr r2, _armboot_start
- ldr r3, _bss_start
- sub r2, r3, r2 /* r2 <- size of armboot */
- add r2, r0, r2 /* r2 <- source end address */
-
-copy_loop:
- ldmia r0!, {r3-r10} /* copy from source address [r0] */
- stmia r1!, {r3-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- ble copy_loop
-
- /* Set up the stack */
-stack_setup:
- ldr r0, _TEXT_BASE /* upper 128 KiB: relocated X-Loader */
- sub sp, r0, #128 /* leave 32 words for abort-stack */
-
-clear_bss:
- ldr r0, _bss_start /* find start of bss segment */
- add r0, r0, #4 /* start at first byte of bss */
- ldr r1, _bss_end /* stop here */
- mov r2, #0x00000000 /* clear */
-
-clbss_l:str r2, [r0] /* clear loop... */
- add r0, r0, #4
- cmp r0, r1
- bne clbss_l
-
- ldr pc, _start_armboot
-
-_start_armboot:
- .word start_armboot
-
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-
-
-cpu_init_crit:
- /*
- * flush v4 I/D caches
- */
- mov r0, #0
- mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
- mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
-
- /*
- * disable MMU stuff and caches
- */
- mrc p15, 0, r0, c1, c0, 0
- bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
- bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
- orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
- orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
- mcr p15, 0, r0, c1, c0, 0
-
- /*
- * Go setup Memory and board specific bits prior to relocation.
- */
- mov ip, lr /* perserve link reg across call */
- bl platformsetup /* go setup pll,mux,memory */
- mov lr, ip /* restore link */
- mov pc, lr /* back to my caller */
-
-/*
- * exception handler
- */
- .align 5
-do_hang:
- ldr sp, _TEXT_BASE /* use 32 words abort stack */
- bl hang /* hang and never return */
-
-
diff --git a/x-loader/drivers/k9f5616.c b/x-loader/drivers/k9f5616.c
deleted file mode 100644
index 4081664..0000000
--- a/x-loader/drivers/k9f5616.c
+++ /dev/null
@@ -1,229 +0,0 @@
-/*
- * (C) Copyright 2004 Texas Instruments
- * Jian Zhang <jzhang@ti.com>
- *
- * Samsung K9F5616Q0C NAND chip driver for an OMAP16xx board
- *
- * This file is based on the following u-boot file:
- * common/cmd_nand.c
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#ifdef CFG_NAND_K9F5616
-
-#define K9F5616_MFR 0xec
-#define K9F5616_ID 0x45
-
-#define ADDR_COLUMN 1
-#define ADDR_PAGE 2
-#define ADDR_COLUMN_PAGE 3
-
-#define PAGE_SIZE 512
-
-static int nand_read_page(u_char *buf, ulong page_addr);
-static int nand_read_oob(u_char * buf, ulong page_addr);
-
-/* JFFS2 512-byte-page ECC layout */
-static u_char ecc_pos[] = {0,1,2,3,6,7};
-static u_char eccvalid_pos = 4;
-
-/* NanD_Command: Send a flash command to the flash chip */
-static int NanD_Command(unsigned char command)
-{
- NAND_CTL_SETCLE(NAND_ADDR);
- WRITE_NAND_COMMAND(command, NAND_ADDR);
- NAND_CTL_CLRCLE(NAND_ADDR);
-
- if(command == NAND_CMD_RESET){
- unsigned char ret_val;
- NanD_Command(NAND_CMD_STATUS);
- do{
- ret_val = READ_NAND(NAND_ADDR);/* wait till ready */
- } while((ret_val & 0x40) != 0x40);
- }
-
- NAND_WAIT_READY();
- return 0;
-}
-
-/* NanD_Address: Set the current address for the flash chip */
-static int NanD_Address(int numbytes, unsigned long ofs)
-{
- int i;
-
- NAND_CTL_SETALE(NAND_ADDR);
-
- if (numbytes == ADDR_COLUMN || numbytes == ADDR_COLUMN_PAGE)
- WRITE_NAND_ADDRESS(ofs, NAND_ADDR);
-
- ofs = ofs >> 8;
-
- if (numbytes == ADDR_PAGE || numbytes == ADDR_COLUMN_PAGE)
- for (i = 0; i < 2; i++, ofs = ofs >> 8)
- WRITE_NAND_ADDRESS(ofs, NAND_ADDR);
-
- NAND_CTL_CLRALE(NAND_ADDR);
-
- NAND_WAIT_READY();
- return 0;
-}
-
-/* read chip mfr and id
- * return 0 if they match board config
- * return 1 if not
- */
-int nand_chip()
-{
- int mfr, id;
-
- NAND_ENABLE_CE();
-
- if (NanD_Command(NAND_CMD_RESET)) {
- printf("Err: RESET\n");
- NAND_DISABLE_CE();
- return 1;
- }
-
- if (NanD_Command(NAND_CMD_READID)) {
- printf("Err: READID\n");
- NAND_DISABLE_CE();
- return 1;
- }
-
- NanD_Address(ADDR_COLUMN, 0);
-
- mfr = READ_NAND(NAND_ADDR);
- id = READ_NAND(NAND_ADDR);
-
- NAND_DISABLE_CE();
-
- return (mfr != K9F5616_MFR || id != K9F5616_ID);
-}
-
-/* read a block data to buf
- * return 1 if the block is bad or ECC error can't be corrected for any page
- * return 0 on sucess
- */
-int nand_read_block(unsigned char *buf, ulong block_addr)
-{
- int i, offset = 0;
- uchar oob_buf[16];
-
- /* check bad block */
- /* 0th and 5th words need be 0xffff */
- if (nand_read_oob(oob_buf, block_addr) ||
-// oob_buf[0] != 0xff || oob_buf[1] != 0xff ||
-// oob_buf[10] != 0xff || oob_buf[11] != 0xff ){
- oob_buf[5] != 0xff){
- printf("Skipped bad block at 0x%x\n", block_addr);
- return 1; /* skip bad block */
- }
-
- /* read the block page by page*/
- for (i=0; i<32; i++){
- if (nand_read_page(buf+offset, block_addr + offset))
- return 1;
- offset += PAGE_SIZE;
- }
-
- return 0;
-}
-
-/* read a page with ECC */
-static int nand_read_page(u_char *buf, ulong page_addr)
-{
- u_char ecc_code[6];
- u_char ecc_calc[3];
- u_char oob_buf[16];
- u_char *p;
- u16 val;
- int cntr;
-
- NAND_ENABLE_CE();
- NanD_Command(NAND_CMD_READ0);
- NanD_Address(ADDR_COLUMN_PAGE, page_addr>>1);
-
- NAND_WAIT_READY();
- p = buf;
- for (cntr = 0; cntr < 256; cntr++){
- val = READ_NAND(NAND_ADDR);
- *p++ = val & 0xff;
- *p++ = val >> 8;
- }
-
- p = oob_buf;
- for (cntr = 0; cntr < 8; cntr++){
- val = READ_NAND(NAND_ADDR);
- *p++ = val & 0xff;
- *p++ = val >> 8;
- }
- NAND_DISABLE_CE(); /* set pin high */
-
- /* Pick the ECC bytes out of the oob data */
- for (cntr = 0; cntr < 6; cntr++)
- ecc_code[cntr] = oob_buf[ecc_pos[cntr]];
-
-
- if ((oob_buf[eccvalid_pos] & 0x0f) != 0x0f) {
- nand_calculate_ecc (buf, &ecc_calc[0]);
- if (nand_correct_data (buf, &ecc_code[0], &ecc_calc[0]) == -1) {
- printf ("ECC Failed, page 0x%08x\n", page_addr);
- return 1;
- }
- }
-
- if ((oob_buf[eccvalid_pos] & 0xf0) != 0xf0) {
- nand_calculate_ecc (buf + 256, &ecc_calc[0]);
- if (nand_correct_data (buf + 256, &ecc_code[3], &ecc_calc[0]) == -1) {
- printf ("ECC Failed, page 0x%08x\n", page_addr+0x100);
- return 1;
- }
- }
-
- return 0;
-}
-
-/* read from the 16 bytes of oob data that correspond to a 512 byte page.
- */
-static int nand_read_oob(u_char *buf, ulong page_addr)
-{
- u16 val;
- int cntr;
-
- NAND_ENABLE_CE(); /* set pin low */
- NanD_Command(NAND_CMD_READOOB);
- NanD_Address(ADDR_COLUMN_PAGE, page_addr>>1);
- NAND_WAIT_READY();
-
- for (cntr = 0; cntr < 8; cntr++){
- val = READ_NAND(NAND_ADDR);
- *buf++ = val & 0xff;
- *buf++ = val >> 8;
- }
-
- NAND_WAIT_READY();
- NAND_DISABLE_CE(); /* set pin high */
-
- return 0;
-}
-
-#endif
diff --git a/x-loader/include/configs/omap1510.h b/x-loader/include/configs/omap1510.h
deleted file mode 100644
index 40deace..0000000
--- a/x-loader/include/configs/omap1510.h
+++ /dev/null
@@ -1,698 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- * OMAP hardware map
- *
- * Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com)
- * Author: RidgeRun, Inc.
- * Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <asm/arch/sizes.h>
-
-/*
- There are 2 sets of general I/O -->
- 1. GPIO (shared between ARM & DSP, configured by ARM)
- 2. MPUIO which can be used only by the ARM.
-
- Base address FFFB:5000 is where the ARM accesses the MPUIO control registers
- (see 7.2.2 of the TRM for MPUIO reg definitions).
-
- Base address E101:5000 is reserved for ARM access of the same MPUIO control
- regs, but via the DSP I/O map. This address is unavailable on 1510.
-
- Base address FFFC:E000 is where the ARM accesses the GPIO config registers
- directly via its own peripheral bus.
-
- Base address E101:E000 is where the ARM can access the same GPIO config
- registers, but the access takes place through the ARM port interface (called
- API or MPUI) via the DSP's peripheral bus (DSP I/O space).
-
- Therefore, the ARM should setup the GPIO regs thru the FFFC:E000 addresses
- instead of the E101:E000 addresses. The DSP has only read access of the pin
- control register, so this may explain the inability to write to E101:E018.
- Try accessing pin control reg at FFFC:E018.
- */
-#define OMAP1510_GPIO_BASE 0xfffce000
-#define OMAP1510_GPIO_START OMAP1510_GPIO_BASE
-#define OMAP1510_GPIO_SIZE SZ_4K
-
-#define OMAP1510_MCBSP1_BASE 0xE1011000
-#define OMAP1510_MCBSP1_SIZE SZ_4K
-#define OMAP1510_MCBSP1_START 0xE1011000
-
-#define OMAP1510_MCBSP2_BASE 0xFFFB1000
-
-#define OMAP1510_MCBSP3_BASE 0xE1017000
-#define OMAP1510_MCBSP3_SIZE SZ_4K
-#define OMAP1510_MCBSP3_START 0xE1017000
-
-/*
- * Where's the flush address (for flushing D and I cache?)
- */
-#define FLUSH_BASE 0xdf000000
-#define FLUSH_BASE_PHYS 0x00000000
-
-#ifndef __ASSEMBLER__
-
-#define PCIO_BASE 0
-
-/*
- * RAM definitions
- */
-#define MAPTOPHYS(a) ((unsigned long)(a) - PAGE_OFFSET)
-#define KERNTOPHYS(a) ((unsigned long)(&a))
-#define KERNEL_BASE (0x10008000)
-#endif
-
-/* macro to get at IO space when running virtually */
-#define IO_ADDRESS(x) ((x))
-
-/* ----------------------------------------------------------------------------
- * OMAP1510 system registers
- * ----------------------------------------------------------------------------
- */
-
-#define OMAP1510_UART1_BASE 0xfffb0000 /* "BLUETOOTH-UART" */
-#define OMAP1510_UART2_BASE 0xfffb0800 /* "MODEM-UART" */
-#define OMAP1510_RTC_BASE 0xfffb4800 /* RTC */
-#define OMAP1510_UART3_BASE 0xfffb9800 /* Shared MPU/DSP UART */
-#define OMAP1510_COM_MCBSP2_BASE 0xffff1000 /* Com McBSP2 */
-#define OMAP1510_AUDIO_MCBSP_BASE 0xffff1800 /* Audio McBSP2 */
-#define OMAP1510_ARMIO_BASE 0xfffb5000 /* keyboard/gpio */
-
-/*
- * OMAP1510 UART3 Registers
- */
-
-#define OMAP_MPU_UART3_BASE 0xFFFB9800 /* UART3 through MPU bus */
-
-/* UART3 Registers Maping through MPU bus */
-
-#define UART3_RHR (OMAP_MPU_UART3_BASE + 0)
-#define UART3_THR (OMAP_MPU_UART3_BASE + 0)
-#define UART3_DLL (OMAP_MPU_UART3_BASE + 0)
-#define UART3_IER (OMAP_MPU_UART3_BASE + 4)
-#define UART3_DLH (OMAP_MPU_UART3_BASE + 4)
-#define UART3_IIR (OMAP_MPU_UART3_BASE + 8)
-#define UART3_FCR (OMAP_MPU_UART3_BASE + 8)
-#define UART3_EFR (OMAP_MPU_UART3_BASE + 8)
-#define UART3_LCR (OMAP_MPU_UART3_BASE + 0x0C)
-#define UART3_MCR (OMAP_MPU_UART3_BASE + 0x10)
-#define UART3_XON1_ADDR1 (OMAP_MPU_UART3_BASE + 0x10)
-#define UART3_XON2_ADDR2 (OMAP_MPU_UART3_BASE + 0x14)
-#define UART3_LSR (OMAP_MPU_UART3_BASE + 0x14)
-#define UART3_TCR (OMAP_MPU_UART3_BASE + 0x18)
-#define UART3_MSR (OMAP_MPU_UART3_BASE + 0x18)
-#define UART3_XOFF1 (OMAP_MPU_UART3_BASE + 0x18)
-#define UART3_XOFF2 (OMAP_MPU_UART3_BASE + 0x1C)
-#define UART3_SPR (OMAP_MPU_UART3_BASE + 0x1C)
-#define UART3_TLR (OMAP_MPU_UART3_BASE + 0x1C)
-#define UART3_MDR1 (OMAP_MPU_UART3_BASE + 0x20)
-#define UART3_MDR2 (OMAP_MPU_UART3_BASE + 0x24)
-#define UART3_SFLSR (OMAP_MPU_UART3_BASE + 0x28)
-#define UART3_TXFLL (OMAP_MPU_UART3_BASE + 0x28)
-#define UART3_RESUME (OMAP_MPU_UART3_BASE + 0x2C)
-#define UART3_TXFLH (OMAP_MPU_UART3_BASE + 0x2C)
-#define UART3_SFREGL (OMAP_MPU_UART3_BASE + 0x30)
-#define UART3_RXFLL (OMAP_MPU_UART3_BASE + 0x30)
-#define UART3_SFREGH (OMAP_MPU_UART3_BASE + 0x34)
-#define UART3_RXFLH (OMAP_MPU_UART3_BASE + 0x34)
-#define UART3_BLR (OMAP_MPU_UART3_BASE + 0x38)
-#define UART3_ACREG (OMAP_MPU_UART3_BASE + 0x3C)
-#define UART3_DIV16 (OMAP_MPU_UART3_BASE + 0x3C)
-#define UART3_SCR (OMAP_MPU_UART3_BASE + 0x40)
-#define UART3_SSR (OMAP_MPU_UART3_BASE + 0x44)
-#define UART3_EBLR (OMAP_MPU_UART3_BASE + 0x48)
-#define UART3_OSC_12M_SEL (OMAP_MPU_UART3_BASE + 0x4C)
-#define UART3_MVR (OMAP_MPU_UART3_BASE + 0x50)
-
-/*
- * Configuration Registers
- */
-#define FUNC_MUX_CTRL_0 0xfffe1000
-#define FUNC_MUX_CTRL_1 0xfffe1004
-#define FUNC_MUX_CTRL_2 0xfffe1008
-#define COMP_MODE_CTRL_0 0xfffe100c
-#define FUNC_MUX_CTRL_3 0xfffe1010
-#define FUNC_MUX_CTRL_4 0xfffe1014
-#define FUNC_MUX_CTRL_5 0xfffe1018
-#define FUNC_MUX_CTRL_6 0xfffe101C
-#define FUNC_MUX_CTRL_7 0xfffe1020
-#define FUNC_MUX_CTRL_8 0xfffe1024
-#define FUNC_MUX_CTRL_9 0xfffe1028
-#define FUNC_MUX_CTRL_A 0xfffe102C
-#define FUNC_MUX_CTRL_B 0xfffe1030
-#define FUNC_MUX_CTRL_C 0xfffe1034
-#define FUNC_MUX_CTRL_D 0xfffe1038
-#define PULL_DWN_CTRL_0 0xfffe1040
-#define PULL_DWN_CTRL_1 0xfffe1044
-#define PULL_DWN_CTRL_2 0xfffe1048
-#define PULL_DWN_CTRL_3 0xfffe104c
-#define GATE_INH_CTRL_0 0xfffe1050
-#define VOLTAGE_CTRL_0 0xfffe1060
-#define TEST_DBG_CTRL_0 0xfffe1070
-
-#define MOD_CONF_CTRL_0 0xfffe1080
-
-/* 1610 Configuration Register */
-#if defined(CONFIG_OMAP1610) || defined(CONFIG_OMAP1710)
-#define USB_OTG_CTRL 0xFFFB040C
-#define USB_TRANSCEIVER_CTRL 0xFFFE1064
-#define PULL_DWN_CTRL_4 0xFFFE10AC
-#define PU_PD_SEL_0 0xFFFE10B4
-#define PU_PD_SEL_1 0xFFFE10B8
-#define PU_PD_SEL_2 0xFFFE10BC
-#define PU_PD_SEL_3 0xFFFE10C0
-#define PU_PD_SEL_4 0xFFFE10C4
-
-#endif
-/*
- * Traffic Controller Memory Interface Registers
- */
-#define TCMIF_BASE 0xfffecc00
-#define IMIF_PRIO (TCMIF_BASE + 0x00)
-#define EMIFS_PRIO_REG (TCMIF_BASE + 0x04)
-#define EMIFF_PRIO_REG (TCMIF_BASE + 0x08)
-#define EMIFS_CONFIG_REG (TCMIF_BASE + 0x0c)
-#define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10)
-#define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14)
-#define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18)
-#define EMIFS_CS3_CONFIG (TCMIF_BASE + 0x1c)
-#define EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20)
-#define EMIFF_MRS (TCMIF_BASE + 0x24)
-#define TC_TIMEOUT1 (TCMIF_BASE + 0x28)
-#define TC_TIMEOUT2 (TCMIF_BASE + 0x2c)
-#define TC_TIMEOUT3 (TCMIF_BASE + 0x30)
-#define TC_ENDIANISM (TCMIF_BASE + 0x34)
-#define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c)
-#define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40)
-
-/*
- * LCD Panel
- */
-#define TI925_LCD_BASE 0xFFFEC000
-#define TI925_LCD_CONTROL (TI925_LCD_BASE)
-#define TI925_LCD_TIMING0 (TI925_LCD_BASE+0x4)
-#define TI925_LCD_TIMING1 (TI925_LCD_BASE+0x8)
-#define TI925_LCD_TIMING2 (TI925_LCD_BASE+0xc)
-#define TI925_LCD_STATUS (TI925_LCD_BASE+0x10)
-#define TI925_LCD_SUBPANEL (TI925_LCD_BASE+0x14)
-
-#define OMAP_LCD_CONTROL TI925_LCD_CONTROL
-
-/*
- * MMC/SD Host Controller Registers
- */
-
-#define OMAP_MMC_CMD 0xFFFB7800 /* MMC Command */
-#define OMAP_MMC_ARGL 0xFFFB7804 /* MMC argument low */
-#define OMAP_MMC_ARGH 0xFFFB7808 /* MMC argument high */
-#define OMAP_MMC_CON 0xFFFB780C /* MMC system configuration */
-#define OMAP_MMC_STAT 0xFFFB7810 /* MMC status */
-#define OMAP_MMC_IE 0xFFFB7814 /* MMC system interrupt enable */
-#define OMAP_MMC_CTO 0xFFFB7818 /* MMC command time-out */
-#define OMAP_MMC_DTO 0xFFFB781C /* MMC data time-out */
-#define OMAP_MMC_DATA 0xFFFB7820 /* MMC TX/RX FIFO data */
-#define OMAP_MMC_BLEN 0xFFFB7824 /* MMC block length */
-#define OMAP_MMC_NBLK 0xFFFB7828 /* MMC number of blocks */
-#define OMAP_MMC_BUF 0xFFFB782C /* MMC buffer configuration */
-#define OMAP_MMC_SPI 0xFFFB7830 /* MMC serial port interface */
-#define OMAP_MMC_SDIO 0xFFFB7834 /* MMC SDIO mode configuration */
-#define OMAP_MMC_SYST 0xFFFB7838 /* MMC system test */
-#define OMAP_MMC_REV 0xFFFB783C /* MMC module version */
-#define OMAP_MMC_RSP0 0xFFFB7840 /* MMC command response 0 */
-#define OMAP_MMC_RSP1 0xFFFB7844 /* MMC command response 1 */
-#define OMAP_MMC_RSP2 0xFFFB7848 /* MMC command response 2 */
-#define OMAP_MMC_RSP3 0xFFFB784C /* MMC command response 3 */
-#define OMAP_MMC_RSP4 0xFFFB7850 /* MMC command response 4 */
-#define OMAP_MMC_RSP5 0xFFFB7854 /* MMC command response 5 */
-#define OMAP_MMC_RSP6 0xFFFB7858 /* MMC command response 6 */
-#define OMAP_MMC_RSP7 0xFFFB785C /* MMC command response 4 */
-
-/* MMC masks */
-
-#define OMAP_MMC_END_OF_CMD (1 << 0) /* End of command phase */
-#define OMAP_MMC_CARD_BUSY (1 << 2) /* Card enter busy state */
-#define OMAP_MMC_BLOCK_RS (1 << 3) /* Block received/sent */
-#define OMAP_MMC_EOF_BUSY (1 << 4) /* Card exit busy state */
-#define OMAP_MMC_DATA_TIMEOUT (1 << 5) /* Data response time-out */
-#define OMAP_MMC_DATA_CRC (1 << 6) /* Date CRC error */
-#define OMAP_MMC_CMD_TIMEOUT (1 << 7) /* Command response time-out */
-#define OMAP_MMC_CMD_CRC (1 << 8) /* Command CRC error */
-#define OMAP_MMC_A_FULL (1 << 10) /* Buffer almost full */
-#define OMAP_MMC_A_EMPTY (1 << 11) /* Buffer almost empty */
-#define OMAP_MMC_OCR_BUSY (1 << 12) /* OCR busy */
-#define OMAP_MMC_CARD_IRQ (1 << 13) /* Card IRQ received */
-#define OMAP_MMC_CARD_ERR (1 << 14) /* Card status error in response */
-
-/* 2.9.2 MPUI Interface Registers FFFE:C900 */
-
-#define MPUI_CTRL_REG (volatile __u32 *)(0xfffec900)
-#define MPUI_DEBUG_ADDR (volatile __u32 *)(0xfffec904)
-#define MPUI_DEBUG_DATA (volatile __u32 *)(0xfffec908)
-#define MPUI_DEBUG_FLAG (volatile __u16 *)(0xfffec90c)
-#define MPUI_STATUS_REG (volatile __u16 *)(0xfffec910)
-#define MPUI_DSP_STATUS_REG (volatile __u16 *)(0xfffec914)
-#define MPUI_DSP_BOOT_CONFIG (volatile __u16 *)(0xfffec918)
-#define MPUI_DSP_API_CONFIG (volatile __u16 *)(0xfffec91c)
-
-/* 2.9.6 Traffic Controller Memory Interface Registers: */
-#define OMAP_IMIF_PRIO_REG 0xfffecc00
-#define OMAP_EMIFS_PRIO_REG 0xfffecc04
-#define OMAP_EMIFF_PRIO_REG 0xfffecc08
-#define OMAP_EMIFS_CONFIG_REG 0xfffecc0c
-#define OMAP_EMIFS_CS0_CONFIG 0xfffecc10
-#define OMAP_EMIFS_CS1_CONFIG 0xfffecc14
-#define OMAP_EMIFS_CS2_CONFIG 0xfffecc18
-#define OMAP_EMIFS_CS3_CONFIG 0xfffecc1c
-#define OMAP_EMIFF_SDRAM_CONFIG 0xfffecc20
-#define OMAP_EMIFF_MRS 0xfffecc24
-#define OMAP_TIMEOUT1 0xfffecc28
-#define OMAP_TIMEOUT2 0xfffecc2c
-#define OMAP_TIMEOUT3 0xfffecc30
-#define OMAP_ENDIANISM 0xfffecc34
-
-/* 2.9.10 EMIF Slow Interface Configuration Register (EMIFS_CONFIG_REG): */
-#define OMAP_EMIFS_CONFIG_FR (1 << 4)
-#define OMAP_EMIFS_CONFIG_PDE (1 << 3)
-#define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2)
-#define OMAP_EMIFS_CONFIG_BM (1 << 1)
-#define OMAP_EMIFS_CONFIG_WP (1 << 0)
-
-/*
- * Memory chunk set aside for the Framebuffer in SRAM
- */
-#define SRAM_FRAMEBUFFER_MEMORY OMAP1510_SRAM_BASE
-
-
-/*
- * DMA
- */
-
-#define OMAP1510_DMA_BASE 0xFFFED800
-#define OMAP_DMA_BASE OMAP1510_DMA_BASE
-
-/* Global Register selection */
-#define NO_GLOBAL_DMA_ACCESS 0
-
-/* Channel select field
- * NOTE: all other channels are linear, chan0 is 0, chan1 is 1, etc...
- */
-#define LCD_CHANNEL 0xc
-
-/* Register Select Field (LCD) */
-#define DMA_LCD_CTRL 0
-#define DMA_LCD_TOP_F1_L 1
-#define DMA_LCD_TOP_F1_U 2
-#define DMA_LCD_BOT_F1_L 3
-#define DMA_LCD_BOT_F1_U 4
-
-#define LCD_FRAME_MODE (1<<0)
-#define LCD_FRAME_IT_IE (1<<1)
-#define LCD_BUS_ERROR_IT_IE (1<<2)
-#define LCD_FRAME_1_IT_COND (1<<3)
-#define LCD_FRAME_2_IT_COND (1<<4)
-#define LCD_BUS_ERROR_IT_COND (1<<5)
-#define LCD_SOURCE_IMIF (1<<6)
-
-/*
- * Real-Time Clock
- */
-
-#define RTC_SECONDS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x00)
-#define RTC_MINUTES (volatile __u8 *)(OMAP1510_RTC_BASE + 0x04)
-#define RTC_HOURS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x08)
-#define RTC_DAYS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x0C)
-#define RTC_MONTHS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x10)
-#define RTC_YEARS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x14)
-#define RTC_CTRL (volatile __u8 *)(OMAP1510_RTC_BASE + 0x40)
-
-
-/* ---------------------------------------------------------------------------
- * OMAP1510 Interrupt Handlers
- * ---------------------------------------------------------------------------
- *
- */
-#define OMAP_IH1_BASE 0xfffecb00
-#define OMAP_IH2_BASE 0xfffe0000
-#define OMAP1510_ITR 0x0
-#define OMAP1510_MASK 0x4
-
-#define INTERRUPT_HANDLER_BASE OMAP_IH1_BASE
-#define INTERRUPT_INPUT_REGISTER OMAP1510_ITR
-#define INTERRUPT_MASK_REGISTER OMAP1510_MASK
-
-
-/* ---------------------------------------------------------------------------
- * OMAP1510 TIMERS
- * ---------------------------------------------------------------------------
- *
- */
-
-#define OMAP1510_32kHz_TIMER_BASE 0xfffb9000
-
-/* 32k Timer Registers */
-#define TIMER32k_CR 0x08
-#define TIMER32k_TVR 0x00
-#define TIMER32k_TCR 0x04
-
-/* 32k Timer Control Register definition */
-#define TIMER32k_TSS (1<<0)
-#define TIMER32k_TRB (1<<1)
-#define TIMER32k_INT (1<<2)
-#define TIMER32k_ARL (1<<3)
-
-/* MPU Timer base addresses */
-#define OMAP1510_MPUTIMER_BASE 0xfffec500
-#define OMAP1510_MPUTIMER_OFF 0x00000100
-
-#define OMAP1510_TIMER1_BASE 0xfffec500
-#define OMAP1510_TIMER2_BASE 0xfffec600
-#define OMAP1510_TIMER3_BASE 0xfffec700
-
-/* MPU Timer Registers */
-#define CNTL_TIMER 0
-#define LOAD_TIM 4
-#define READ_TIM 8
-
-/* CNTL_TIMER register bits */
-#define MPUTIM_FREE (1<<6)
-#define MPUTIM_CLOCK_ENABLE (1<<5)
-#define MPUTIM_PTV_MASK (0x7<<PTV_BIT)
-#define MPUTIM_PTV_BIT 2
-#define MPUTIM_AR (1<<1)
-#define MPUTIM_ST (1<<0)
-
-/* ---------------------------------------------------------------------------
- * OMAP1510 GPIO (SHARED)
- * ---------------------------------------------------------------------------
- *
- */
-#define GPIO_DATA_INPUT_REG (OMAP1510_GPIO_BASE + 0x0)
-#define GPIO_DATA_OUTPUT_REG (OMAP1510_GPIO_BASE + 0x4)
-#define GPIO_DIR_CONTROL_REG (OMAP1510_GPIO_BASE + 0x8)
-#define GPIO_INT_CONTROL_REG (OMAP1510_GPIO_BASE + 0xc)
-#define GPIO_INT_MASK_REG (OMAP1510_GPIO_BASE + 0x10)
-#define GPIO_INT_STATUS_REG (OMAP1510_GPIO_BASE + 0x14)
-#define GPIO_PIN_CONTROL_REG (OMAP1510_GPIO_BASE + 0x18)
-
-
-/* ---------------------------
- * OMAP1510 MPUIO (ARM only)
- *----------------------------
- */
-#define OMAP1510_MPUIO_BASE 0xFFFB5000
-#define MPUIO_DATA_INPUT_REG (OMAP1510_MPUIO_BASE + 0x0)
-#define MPUIO_DATA_OUTPUT_REG (OMAP1510_MPUIO_BASE + 0x4)
-#define MPUIO_DIR_CONTROL_REG (OMAP1510_MPUIO_BASE + 0x8)
-
-/* ---------------------------------------------------------------------------
- * OMAP1510 TIPB (only)
- * ---------------------------------------------------------------------------
- *
- */
-#define TIPB_PUBLIC_CNTL_BASE 0xfffed300
-#define MPU_PUBLIC_TIPB_CNTL_REG (TIPB_PUBLIC_CNTL_BASE + 0x8)
-#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00
-#define MPU_PRIVATE_TIPB_CNTL_REG (TIPB_PRIVATE_CNTL_BASE + 0x8)
-
-/*
- * ---------------------------------------------------------------------------
- * OMAP1510 Camera Interface
- * ---------------------------------------------------------------------------
- */
-#define CAMERA_BASE (IO_BASE + 0x6800)
-#define CAM_CTRLCLOCK_REG (CAMERA_BASE + 0x00)
-#define CAM_IT_STATUS_REG (CAMERA_BASE + 0x04)
-#define CAM_MODE_REG (CAMERA_BASE + 0x08)
-#define CAM_STATUS_REG (CAMERA_BASE + 0x0C)
-#define CAM_CAMDATA_REG (CAMERA_BASE + 0x10)
-#define CAM_GPIO_REG (CAMERA_BASE + 0x14)
-#define CAM_PEAK_CTR_REG (CAMERA_BASE + 0x18)
-
-#if 0
-#ifndef __ASSEMBLY__
-typedef struct {
- __u32 ctrlclock;
- __u32 it_status;
- __u32 mode;
- __u32 status;
- __u32 camdata;
- __u32 gpio;
- __u32 peak_counter;
-} camera_regs_t;
-#endif
-#endif
-
-/* CTRLCLOCK bit shifts */
-#define FOSCMOD_BIT 0
-#define FOSCMOD_MASK (0x7 << FOSCMOD_BIT)
-#define FOSCMOD_12MHz 0x0
-#define FOSCMOD_6MHz 0x2
-#define FOSCMOD_9_6MHz 0x4
-#define FOSCMOD_24MHz 0x5
-#define FOSCMOD_8MHz 0x6
-#define POLCLK (1<<3)
-#define CAMEXCLK_EN (1<<4)
-#define MCLK_EN (1<<5)
-#define DPLL_EN (1<<6)
-#define LCLK_EN (1<<7)
-
-/* IT_STATUS bit shifts */
-#define V_UP (1<<0)
-#define V_DOWN (1<<1)
-#define H_UP (1<<2)
-#define H_DOWN (1<<3)
-#define FIFO_FULL (1<<4)
-#define DATA_XFER (1<<5)
-
-/* MODE bit shifts */
-#define CAMOSC (1<<0)
-#define IMGSIZE_BIT 1
-#define IMGSIZE_MASK (0x3 << IMGSIZE_BIT)
-#define IMGSIZE_CIF (0x0 << IMGSIZE_BIT) /* 352x288 */
-#define IMGSIZE_QCIF (0x1 << IMGSIZE_BIT) /* 176x144 */
-#define IMGSIZE_VGA (0x2 << IMGSIZE_BIT) /* 640x480 */
-#define IMGSIZE_QVGA (0x3 << IMGSIZE_BIT) /* 320x240 */
-#define ORDERCAMD (1<<3)
-#define EN_V_UP (1<<4)
-#define EN_V_DOWN (1<<5)
-#define EN_H_UP (1<<6)
-#define EN_H_DOWN (1<<7)
-#define EN_DMA (1<<8)
-#define THRESHOLD (1<<9)
-#define THRESHOLD_BIT 9
-#define THRESHOLD_MASK (0x7f<<9)
-#define EN_NIRQ (1<<16)
-#define EN_FIFO_FULL (1<<17)
-#define RAZ_FIFO (1<<18)
-
-/* STATUS bit shifts */
-#define VSTATUS (1<<0)
-#define HSTATUS (1<<1)
-
-/* GPIO bit shifts */
-#define CAM_RST (1<<0)
-
-
-/*********************
- * Watchdog timer.
- *********************/
-#define WDTIM_BASE 0xfffec800
-#define WDTIM_CONTROL (WDTIM_BASE+0x00)
-#define WDTIM_LOAD (WDTIM_BASE+0x04)
-#define WDTIM_READ (WDTIM_BASE+0x04)
-#define WDTIM_MODE (WDTIM_BASE+0x08)
-
-/* Values to write to mode register to disable the watchdog function. */
-#define DISABLE_SEQ1 0xF5
-#define DISABLE_SEQ2 0xA0
-
-/* WDTIM_CONTROL bit definitions. */
-#define WDTIM_CONTROL_ST BIT7
-
-
-/* ---------------------------------------------------------------------------
- * Differentiating processor versions for those who care.
- * ---------------------------------------------------------------------------
- *
- */
-#define OMAP1509 0
-#define OMAP1510 1
-
-#define OMAP1510_ID_CODE_REG 0xfffed404
-
-#ifndef __ASSEMBLY__
-int cpu_type(void);
-#endif
-
-/*
- * EVM Implementation Specifics.
- *
- * *** NOTE ***
- * Any definitions in these files should be prefixed by an identifier -
- * eg. OMAP1510P1_FLASH0_BASE .
- *
- */
-#ifdef CONFIG_OMAP_INNOVATOR
-#include "innovator.h"
-#endif
-
-#ifdef CONFIG_OMAP_1510P1
-#include "omap1510p1.h"
-#endif
-
-/*****************************************************************************/
-
-#define CLKGEN_RESET_BASE (0xfffece00)
-#define ARM_CKCTL (volatile __u16 *)(CLKGEN_RESET_BASE + 0x0)
-#define ARM_IDLECT1 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x4)
-#define ARM_IDLECT2 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x8)
-#define ARM_EWUPCT (volatile __u16 *)(CLKGEN_RESET_BASE + 0xC)
-#define ARM_RSTCT1 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x10)
-#define ARM_RSTCT2 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x14)
-#define ARM_SYSST (volatile __u16 *)(CLKGEN_RESET_BASE + 0x18)
-
-
-#define CK_CLKIN 12 /* MHz */
-#define CK_RATEF 1
-#define CK_IDLEF 2
-#define CK_ENABLEF 4
-#define CK_SELECTF 8
-#ifndef __ASSEMBLER__
-#define CK_DPLL1 ((volatile __u16 *)0xfffecf00)
-#else
-#define CK_DPLL1 (0xfffecf00)
-#endif
-#define SETARM_IDLE_SHIFT
-
-/* ARM_CKCTL bit shifts */
-#define PERDIV 0
-#define LCDDIV 2
-#define ARMDIV 4
-#define DSPDIV 6
-#define TCDIV 8
-#define DSPMMUDIV 10
-#define ARM_TIMXO 12
-#define EN_DSPCK 13
-#define ARM_INTHCK_SEL 14 /* REVISIT -- where is this used? */
-
-#define ARM_CKCTL_RSRVD_BIT15 (1 << 15)
-#define ARM_CKCTL_ARM_INTHCK_SEL (1 << 14)
-#define ARM_CKCTL_EN_DSPCK (1 << 13)
-#define ARM_CKCTL_ARM_TIMXO (1 << 12)
-#define ARM_CKCTL_DSPMMU_DIV1 (1 << 11)
-#define ARM_CKCTL_DSPMMU_DIV2 (1 << 10)
-#define ARM_CKCTL_TCDIV1 (1 << 9)
-#define ARM_CKCTL_TCDIV2 (1 << 8)
-#define ARM_CKCTL_DSPDIV1 (1 << 7)
-#define ARM_CKCTL_DSPDIV0 (1 << 6)
-#define ARM_CKCTL_ARMDIV1 (1 << 5)
-#define ARM_CKCTL_ARMDIV0 (1 << 4)
-#define ARM_CKCTL_LCDDIV1 (1 << 3)
-#define ARM_CKCTL_LCDDIV0 (1 << 2)
-#define ARM_CKCTL_PERDIV1 (1 << 1)
-#define ARM_CKCTL_PERDIV0 (1 << 0)
-
-/* ARM_IDLECT1 bit shifts */
-#define IDLWDT_ARM 0
-#define IDLXORP_ARM 1
-#define IDLPER_ARM 2
-#define IDLLCD_ARM 3
-#define IDLLB_ARM 4
-#define IDLHSAB_ARM 5
-#define IDLIF_ARM 6
-#define IDLDPLL_ARM 7
-#define IDLAPI_ARM 8
-#define IDLTIM_ARM 9
-#define SETARM_IDLE 11
-
-/* ARM_IDLECT2 bit shifts */
-#define EN_WDTCK 0
-#define EN_XORPCK 1
-#define EN_PERCK 2
-#define EN_LCDCK 3
-#define EN_LBCK 4
-#define EN_HSABCK 5
-#define EN_APICK 6
-#define EN_TIMCK 7
-#define DMACK_REQ 8
-#define EN_GPIOCK 9
-#define EN_LBFREECK 10
-
-#define ARM_RSTCT1_SW_RST (1 << 3)
-#define ARM_RSTCT1_DSP_RST (1 << 2)
-#define ARM_RSTCT1_DSP_EN (1 << 1)
-#define ARM_RSTCT1_ARM_RST (1 << 0)
-
-/* ARM_RSTCT2 bit shifts */
-#define EN_PER 0
-
-#define ARM_SYSST_RSRVD_BIT15 (1 << 15)
-#define ARM_SYSST_RSRVD_BIT14 (1 << 14)
-#define ARM_SYSST_CLOCK_SELECT2 (1 << 13)
-#define ARM_SYSST_CLOCK_SELECT1 (1 << 12)
-#define ARM_SYSST_CLOCK_SELECT0 (1 << 11)
-#define ARM_SYSST_RSRVD_BIT10 (1 << 10)
-#define ARM_SYSST_RSRVD_BIT9 (1 << 9)
-#define ARM_SYSST_RSRVD_BIT8 (1 << 8)
-#define ARM_SYSST_RSRVD_BIT7 (1 << 7)
-#define ARM_SYSST_IDLE_DSP (1 << 6)
-#define ARM_SYSST_POR (1 << 5)
-#define ARM_SYSST_EXT_RST (1 << 4)
-#define ARM_SYSST_ARM_MCRST (1 << 3)
-#define ARM_SYSST_ARM_WDRST (1 << 2)
-#define ARM_SYSST_GLOB_SWRST (1 << 1)
-#define ARM_SYSST_DSP_WDRST (1 << 0)
-
-/* Table 15-23. DPLL Control Registers: */
-#define DPLL_CTL_REG (volatile __u16 *)(0xfffecf00)
-
-/* Table 15-24. Control Register (CTL_REG): */
-
-#define DPLL_CTL_REG_IOB (1 << 13)
-#define DPLL_CTL_REG_PLL_MULT Fld(5,0)
-
-/*****************************************************************************/
-
-/* OMAP INTERRUPT REGISTERS */
-#define IRQ_ITR 0x00
-#define IRQ_MIR 0x04
-#define IRQ_SIR_IRQ 0x10
-#define IRQ_SIR_FIQ 0x14
-#define IRQ_CONTROL_REG 0x18
-#define IRQ_ISR 0x9c
-#define IRQ_ILR0 0x1c
-
-#define REG_IHL1_MIR (OMAP_IH1_BASE+IRQ_MIR)
-#define REG_IHL2_MIR (OMAP_IH2_BASE+IRQ_MIR)
-
-/* INTERRUPT LEVEL REGISTER BITS */
-#define ILR_PRIORITY_MASK (0x3c)
-#define ILR_PRIORITY_SHIFT (2)
-#define ILR_LEVEL_TRIGGER (1<<1)
-#define ILR_FIQ (1<<0)
-
-#define IRQ_LEVEL_INT 1
-#define IRQ_EDGE_INT 0
diff --git a/x-loader/include/configs/omap1710h3.h b/x-loader/include/configs/omap1710h3.h
deleted file mode 100644
index 6a881bd..0000000
--- a/x-loader/include/configs/omap1710h3.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments.
- * Jian Zhang <jzhang@ti.com>, Kshitij Gupta <kshitij@ti.com>
- * X-Loader Configuation settings for the TI OMAP H3 board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* exactly uncomment one */
-#define CFG_BOOT_CS0 /* ROM code -> signed X-Loader in NNAD */
-//#define CFG_BOOT_CS3 /* unsigned X-loader in NOR for development */
-
-/* serial printf facility takes about 3.5K */
-#define CFG_PRINTF
-//#undef CFG_PRINTF
-
-/* uncomment it if you need timer based udelay(). it takes about 250 bytes */
-//#define CFG_UDELAY
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
-#define CONFIG_OMAP 1 /* in a TI OMAP core */
-#define CONFIG_OMAP1710 1 /* which is in a 1710 */
-#define CONFIG_H3_OMAP1710 1 /* a H3 Board */
-
-/* input clock of PLL */
-/* the OMAP1710 H3 has 12MHz input clock */
-#define CONFIG_SYS_CLK_FREQ 12000000
-
-
-#ifdef CFG_PRINTF
-
-#define CFG_NS16550
-#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE (-4)
-#define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */
-#define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart on helen */
-
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-#endif /* CFG_PRINTF */
-
-#include <configs/omap1510.h>
-
-/*
- * Miscellaneous configurable options
- */
-#define CFG_PBSIZE 256
-#define CFG_LOADADDR 0x11000000
-
-#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
-
-/* The 1710 has 6 timers, they can be driven by the RefClk (12Mhz) or by
- * DPLL1. This time is further subdivided by a local divisor.
- */
-#define CFG_TIMERBASE 0xFFFEC500 /* use timer 1 */
-#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */
-#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE (128*1024) /* regular stack */
-
-/*-----------------------------------------------------------------------
- * Board NAND Info.
- */
-#define CFG_NAND_K9F5616 /* Samsung 16-bit 32MB chip */
-
-#ifdef CFG_BOOT_CS0
-#define NAND_ADDR 0x0c000000 /* physical address to access nand at CS3*/
-#else
-#define NAND_ADDR 0x0a000000 /* physical address to access nand at CS2B*/
-#endif
-
-/* H3 NAND is partitioned:
- * 0x0000000 - 0x0010000 Booting Image
- * 0x0010000 - 0x0050000 U-Boot Image
- * 0x0050000 - 0x0080000 U-Boot Env Data (X-loader doesn't care)
- * 0x0080000 - 0x2000000 depends on application
- */
-#define NAND_UBOOT_START 0x0010000
-#define NAND_UBOOT_END 0x0050000
-#define NAND_BLOCK_SIZE 0x4000
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr + 2) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr + 4) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u16 *)((unsigned long)adr) = (__u16)(d); } while(0)
-#define READ_NAND(adr) ((volatile __u16)(*(volatile __u16 *)(unsigned long)adr))
-
-#define GPIO1_DATAIN 0xfffbe42c
-#define NAND_WAIT_READY() while(!((*(volatile __u16 *)(GPIO1_DATAIN) & 0x0400) == 0x0400));
-
-#define NAND_CTL_CLRALE(adr)
-#define NAND_CTL_SETALE(adr)
-#define NAND_CTL_CLRCLE(adr)
-#define NAND_CTL_SETCLE(adr)
-#define NAND_DISABLE_CE()
-#define NAND_ENABLE_CE()
-
-
-#endif /* __CONFIG_H */
generated by cgit v1.1 at 2024-12-22 11:35:18 +0000