diff options
Diffstat (limited to 'board/omap4430panda')
| -rw-r--r-- | board/omap4430panda/Makefile | 53 | ||||
| -rw-r--r-- | board/omap4430panda/clock.c | 804 | ||||
| -rw-r--r-- | board/omap4430panda/config.mk | 21 | ||||
| -rw-r--r-- | board/omap4430panda/omap4430panda.c | 1235 | ||||
| -rw-r--r-- | board/omap4430panda/platform.S | 51 | ||||
| -rw-r--r-- | board/omap4430panda/syslib.c | 73 |
6 files changed, 2237 insertions, 0 deletions
diff --git a/board/omap4430panda/Makefile b/board/omap4430panda/Makefile new file mode 100644 index 0000000..6b6f9be --- /dev/null +++ b/board/omap4430panda/Makefile @@ -0,0 +1,53 @@ +# +# (C) Copyright 2009 +# Texas Instruments, <www.ti.com> +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License +# version 2 as published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := omap4430panda.o clock.o syslib.o +SOBJS := platform.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/omap4430panda/clock.c b/board/omap4430panda/clock.c new file mode 100644 index 0000000..792e5d6 --- /dev/null +++ b/board/omap4430panda/clock.c @@ -0,0 +1,804 @@ +/* + * (C) Copyright 2009 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * Rajendra Nayak <rnayak@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/cpu.h> +#include <asm/io.h> +#include <asm/arch/bits.h> +#include <asm/arch/clocks.h> +#include <asm/arch/mem.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/sys_info.h> +#include <asm/arch/clocks443x.h> +#include <command.h> + +#define CONFIG_OMAP4_SDC 1 + +/* Used to index into DPLL parameter tables */ +struct dpll_param { + unsigned int m; + unsigned int n; + unsigned int m2; + unsigned int m3; + unsigned int m4; + unsigned int m5; + unsigned int m6; + unsigned int m7; +}; + +/* Tables having M,N,M2 et al values for different sys_clk speeds + * This table is generated only for OPP100 + * The tables are organized as follows: + * Rows : 1 - 12M, 2 - 13M, 3 - 16.8M, 4 - 19.2M, 5 - 26M, 6 - 27M, 7 - 38.4M + */ + +/* MPU parameters */ +struct dpll_param mpu_dpll_param[7] = { + /* 12M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 13M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 16.8M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 19.2M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 26M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 27M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 38.4M values */ +#ifdef CONFIG_MPU_600 + /* RUN MPU @ 600 MHz */ + {0x7d, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}, +#elif CONFIG_MPU_1000 + {0x69, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}, +#else + {0x1a, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}, +#endif +}; + +/* IVA parameters */ +struct dpll_param iva_dpll_param[7] = { + /* 12M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 13M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 16.8M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 19.2M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 26M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 27M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 38.4M values */ +#ifdef CONFIG_OMAP4_SDC + {0x61, 0x03, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00}, +#else + {0x61, 0x03, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00}, +#endif +}; + +/* CORE parameters */ +struct dpll_param core_dpll_param[7] = { + /* 12M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 13M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 16.8M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 19.2M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 26M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 27M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 38.4M values - DDR@200MHz*/ + {0x7d, 0x05, 0x02, 0x05, 0x08, 0x04, 0x06, 0x05}, +}; + +/* CORE parameters - ES2.1 */ +struct dpll_param core_dpll_param_ddr400[7] = { + /* 12M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 13M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 16.8M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 19.2M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 26M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 27M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 38.4M values - DDR@400MHz*/ + {0x7d, 0x05, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05}, +}; + +/* CORE parameters for L3 at 190 MHz - For ES1 only*/ +struct dpll_param core_dpll_param_l3_190[7] = { + /* 12M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 13M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 16.8M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 19.2M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 26M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 27M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 38.4M values */ +#ifdef CONFIG_OMAP4_SDC +#ifdef CORE_190MHZ + {0x1f0, 0x18, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05}, +#else /* Default CORE @166MHz */ + {0x1b0, 0x18, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05}, +#endif +#else + {0x7d, 0x05, 0x01, 0x05, 0x08, 0x04, 0x06, 0x08}, +#endif +}; + +/* PER parameters */ +struct dpll_param per_dpll_param[7] = { + /* 12M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 13M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 16.8M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 19.2M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 26M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 27M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 38.4M values */ +#if 0 + /* SDC settings */ + {0x0a, 0x00, 0x04, 0x03, 0x06, 0x05, 0x02, 0x03}, +#endif + {0x14, 0x00, 0x08, 0x06, 0x0c, 0x09, 0x04, 0x05}, +}; + +/* ABE parameters */ +struct dpll_param abe_dpll_param[7] = { + /* 12M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 13M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 16.8M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 19.2M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 26M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 27M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 38.4M values */ +#ifdef CONFIG_OMAP4_SDC + {0x40, 0x18, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0}, +#else + {0x40, 0x18, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0}, +#endif +}; + +/* USB parameters */ +struct dpll_param usb_dpll_param[7] = { + /* 12M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 13M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 16.8M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 19.2M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 26M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 27M values */ + {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, + /* 38.4M values */ +#ifdef CONFIG_OMAP4_SDC + {0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0}, +#else + {0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0}, +#endif +}; + +typedef struct dpll_param dpll_param; + +static void configure_mpu_dpll(u32 clk_index) +{ + dpll_param *dpll_param_p; + + /* Unlock the MPU dpll */ + sr32(CM_CLKMODE_DPLL_MPU, 0, 3, PLL_MN_POWER_BYPASS); + wait_on_value(BIT0, 0, CM_IDLEST_DPLL_MPU, LDELAY); + + /* Program MPU DPLL */ + dpll_param_p = &mpu_dpll_param[clk_index]; + + sr32(CM_AUTOIDLE_DPLL_MPU, 0, 3, 0x0); /* Disable DPLL autoidle */ + + /* Set M,N,M2 values */ + sr32(CM_CLKSEL_DPLL_MPU, 8, 11, dpll_param_p->m); + sr32(CM_CLKSEL_DPLL_MPU, 0, 6, dpll_param_p->n); + sr32(CM_DIV_M2_DPLL_MPU, 0, 5, dpll_param_p->m2); + sr32(CM_DIV_M2_DPLL_MPU, 8, 1, 0x1); + + /* Lock the mpu dpll */ + sr32(CM_CLKMODE_DPLL_MPU, 0, 3, PLL_LOCK | 0x10); + wait_on_value(BIT0, 1, CM_IDLEST_DPLL_MPU, LDELAY); + + return; +} + +static void configure_iva_dpll(u32 clk_index) +{ + dpll_param *dpll_param_p; + + /* Unlock the IVA dpll */ + sr32(CM_CLKMODE_DPLL_IVA, 0, 3, PLL_MN_POWER_BYPASS); + wait_on_value(BIT0, 0, CM_IDLEST_DPLL_IVA, LDELAY); + + /* CM_BYPCLK_DPLL_IVA = CORE_X2_CLK/2 */ + sr32(CM_BYPCLK_DPLL_IVA, 0, 2, 0x1); + + /* Program IVA DPLL */ + dpll_param_p = &iva_dpll_param[clk_index]; + + sr32(CM_AUTOIDLE_DPLL_IVA, 0, 3, 0x0); /* Disable DPLL autoidle */ + + /* Set M,N,M4,M5 */ + sr32(CM_CLKSEL_DPLL_IVA, 8, 11, dpll_param_p->m); + sr32(CM_CLKSEL_DPLL_IVA, 0, 7, dpll_param_p->n); + sr32(CM_DIV_M4_DPLL_IVA, 0, 5, dpll_param_p->m4); + sr32(CM_DIV_M4_DPLL_IVA, 8, 1, 0x1); + sr32(CM_DIV_M5_DPLL_IVA, 0, 5, dpll_param_p->m5); + sr32(CM_DIV_M5_DPLL_IVA, 8, 1, 0x1); + + /* Lock the iva dpll */ + sr32(CM_CLKMODE_DPLL_IVA, 0, 3, PLL_LOCK); + wait_on_value(BIT0, 1, CM_IDLEST_DPLL_IVA, LDELAY); + + return; +} + +static void configure_per_dpll(u32 clk_index) +{ + dpll_param *dpll_param_p; + + /* Unlock the PER dpll */ + sr32(CM_CLKMODE_DPLL_PER, 0, 3, PLL_MN_POWER_BYPASS); + wait_on_value(BIT0, 0, CM_IDLEST_DPLL_PER, LDELAY); + + /* Program PER DPLL */ + dpll_param_p = &per_dpll_param[clk_index]; + + /* Disable autoidle */ + sr32(CM_AUTOIDLE_DPLL_PER, 0, 3, 0x0); + + sr32(CM_CLKSEL_DPLL_PER, 8, 11, dpll_param_p->m); + sr32(CM_CLKSEL_DPLL_PER, 0, 6, dpll_param_p->n); + sr32(CM_DIV_M2_DPLL_PER, 0, 5, dpll_param_p->m2); + sr32(CM_DIV_M3_DPLL_PER, 0, 5, dpll_param_p->m3); + sr32(CM_DIV_M4_DPLL_PER, 0, 5, dpll_param_p->m4); + sr32(CM_DIV_M5_DPLL_PER, 0, 5, dpll_param_p->m5); + sr32(CM_DIV_M6_DPLL_PER, 0, 5, dpll_param_p->m6); + sr32(CM_DIV_M7_DPLL_PER, 0, 5, dpll_param_p->m7); + +// if(omap_revision() == OMAP4430_ES1_0) +// { + /* Do this only on ES1.0 */ + sr32(CM_DIV_M2_DPLL_PER, 8, 1, 0x1); + sr32(CM_DIV_M3_DPLL_PER, 8, 1, 0x1); + sr32(CM_DIV_M4_DPLL_PER, 8, 1, 0x1); + sr32(CM_DIV_M5_DPLL_PER, 8, 1, 0x1); + sr32(CM_DIV_M6_DPLL_PER, 8, 1, 0x1); + sr32(CM_DIV_M7_DPLL_PER, 8, 1, 0x1); +// } + + /* Lock the per dpll */ + sr32(CM_CLKMODE_DPLL_PER, 0, 3, PLL_LOCK); + wait_on_value(BIT0, 1, CM_IDLEST_DPLL_PER, LDELAY); + + return; +} + +static void configure_abe_dpll(u32 clk_index) +{ + dpll_param *dpll_param_p; + + /* Select sys_clk as ref clk for ABE dpll */ + sr32(CM_ABE_PLL_REF_CLKSEL, 0, 32, 0x0); + + /* Enable slimbus and pad clocks */ + sr32(CM_CLKSEL_ABE, 0, 32, 0x500); + + /* Unlock the ABE dpll */ + sr32(CM_CLKMODE_DPLL_ABE, 0, 3, PLL_MN_POWER_BYPASS); + wait_on_value(BIT0, 0, CM_IDLEST_DPLL_ABE, LDELAY); + + /* Program ABE DPLL */ + dpll_param_p = &abe_dpll_param[clk_index]; + + /* Disable autoidle */ + sr32(CM_AUTOIDLE_DPLL_ABE, 0, 3, 0x0); + + sr32(CM_CLKSEL_DPLL_ABE, 8, 11, dpll_param_p->m); + sr32(CM_CLKSEL_DPLL_ABE, 0, 6, dpll_param_p->n); + + /* Force DPLL CLKOUTHIF to stay enabled */ + sr32(CM_DIV_M2_DPLL_ABE, 0, 32, 0x500); + sr32(CM_DIV_M2_DPLL_ABE, 0, 5, dpll_param_p->m2); + sr32(CM_DIV_M2_DPLL_ABE, 8, 1, 0x1); + /* Force DPLL CLKOUTHIF to stay enabled */ + sr32(CM_DIV_M3_DPLL_ABE, 0, 32, 0x100); + sr32(CM_DIV_M3_DPLL_ABE, 0, 5, dpll_param_p->m3); + sr32(CM_DIV_M3_DPLL_ABE, 8, 1, 0x1); + + /* Lock the abe dpll */ + sr32(CM_CLKMODE_DPLL_ABE, 0, 3, PLL_LOCK); + wait_on_value(BIT0, 1, CM_IDLEST_DPLL_ABE, LDELAY); + + return; +} + +static void configure_usb_dpll(u32 clk_index) +{ + dpll_param *dpll_param_p; + + /* Select the 60Mhz clock 480/8 = 60*/ + sr32(CM_CLKSEL_USB_60MHz, 0, 32, 0x1); + + /* Unlock the USB dpll */ + sr32(CM_CLKMODE_DPLL_USB, 0, 3, PLL_MN_POWER_BYPASS); + wait_on_value(BIT0, 0, CM_IDLEST_DPLL_USB, LDELAY); + + /* Program USB DPLL */ + dpll_param_p = &usb_dpll_param[clk_index]; + + /* Disable autoidle */ + sr32(CM_AUTOIDLE_DPLL_USB, 0, 3, 0x0); + + sr32(CM_CLKSEL_DPLL_USB, 8, 11, dpll_param_p->m); + sr32(CM_CLKSEL_DPLL_USB, 0, 6, dpll_param_p->n); + + /* Force DPLL CLKOUT to stay active */ + sr32(CM_DIV_M2_DPLL_USB, 0, 32, 0x100); + sr32(CM_DIV_M2_DPLL_USB, 0, 5, dpll_param_p->m2); + sr32(CM_DIV_M2_DPLL_USB, 8, 1, 0x1); + sr32(CM_CLKDCOLDO_DPLL_USB, 8, 1, 0x1); + + /* Lock the usb dpll */ + sr32(CM_CLKMODE_DPLL_USB, 0, 3, PLL_LOCK); + wait_on_value(BIT0, 1, CM_IDLEST_DPLL_USB, LDELAY); + + /* force enable the CLKDCOLDO clock */ + sr32(CM_CLKDCOLDO_DPLL_USB, 0, 32, 0x100); + + return; +} + +static void configure_core_dpll(clk_index) +{ + dpll_param *dpll_param_p; + + /* Get the sysclk speed from cm_sys_clksel + * Set it to 38.4 MHz, in case ROM code is bypassed + */ + if (!clk_index) + return; + + /* CORE_CLK=CORE_X2_CLK/2, L3_CLK=CORE_CLK/2, L4_CLK=L3_CLK/2 */ + sr32(CM_CLKSEL_CORE, 0, 32, 0x110); + + /* Unlock the CORE dpll */ + sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_MN_POWER_BYPASS); + wait_on_value(BIT0, 0, CM_IDLEST_DPLL_CORE, LDELAY); + + /* Program Core DPLL */ + if(omap_revision() == OMAP4430_ES1_0) + dpll_param_p = &core_dpll_param_l3_190[clk_index]; + else if(omap_revision() == OMAP4430_ES2_0) + dpll_param_p = &core_dpll_param[clk_index]; + else if(omap_revision() == OMAP4430_ES2_1) + dpll_param_p = &core_dpll_param_ddr400[clk_index]; + + /* Disable autoidle */ + sr32(CM_AUTOIDLE_DPLL_CORE, 0, 3, 0x0); + + sr32(CM_CLKSEL_DPLL_CORE, 8, 11, dpll_param_p->m); + sr32(CM_CLKSEL_DPLL_CORE, 0, 6, dpll_param_p->n); + sr32(CM_DIV_M2_DPLL_CORE, 0, 5, dpll_param_p->m2); + sr32(CM_DIV_M3_DPLL_CORE, 0, 5, dpll_param_p->m3); + sr32(CM_DIV_M4_DPLL_CORE, 0, 5, dpll_param_p->m4); + sr32(CM_DIV_M5_DPLL_CORE, 0, 5, dpll_param_p->m5); + sr32(CM_DIV_M6_DPLL_CORE, 0, 5, dpll_param_p->m6); + sr32(CM_DIV_M7_DPLL_CORE, 0, 5, dpll_param_p->m7); + + if(omap_revision() == OMAP4430_ES1_0) + { + /* Do this only on ES1.0 */ + sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1); + sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1); + sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1); + sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1); + sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x1); + sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1); + } + + + /* Lock the core dpll */ + sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_LOCK); + wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY); + + return; +} + + +void configure_core_dpll_no_lock(void) +{ + dpll_param *dpll_param_p; + u32 clk_index; + + /* Get the sysclk speed from cm_sys_clksel + * Set it to 38.4 MHz, in case ROM code is bypassed + */ + __raw_writel(0x7,CM_SYS_CLKSEL); + clk_index = 7; + + clk_index = clk_index - 1; + /* CORE_CLK=CORE_X2_CLK/2, L3_CLK=CORE_CLK/2, L4_CLK=L3_CLK/2 */ + sr32(CM_CLKSEL_CORE, 0, 32, 0x110); + + /* Unlock the CORE dpll */ + sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_MN_POWER_BYPASS); + wait_on_value(BIT0, 0, CM_IDLEST_DPLL_CORE, LDELAY); + + /* Program Core DPLL */ + if(omap_revision() == OMAP4430_ES1_0) + dpll_param_p = &core_dpll_param_l3_190[clk_index]; + else if(omap_revision() == OMAP4430_ES2_0) + dpll_param_p = &core_dpll_param[clk_index]; + else if(omap_revision() == OMAP4430_ES2_1) + dpll_param_p = &core_dpll_param_ddr400[clk_index]; + + /* Disable autoidle */ + sr32(CM_AUTOIDLE_DPLL_CORE, 0, 3, 0x0); + + sr32(CM_CLKSEL_DPLL_CORE, 8, 11, dpll_param_p->m); + sr32(CM_CLKSEL_DPLL_CORE, 0, 6, dpll_param_p->n); + sr32(CM_DIV_M2_DPLL_CORE, 0, 5, dpll_param_p->m2); + sr32(CM_DIV_M3_DPLL_CORE, 0, 5, dpll_param_p->m3); + sr32(CM_DIV_M4_DPLL_CORE, 0, 5, dpll_param_p->m4); + sr32(CM_DIV_M5_DPLL_CORE, 0, 5, dpll_param_p->m5); + sr32(CM_DIV_M6_DPLL_CORE, 0, 5, dpll_param_p->m6); + sr32(CM_DIV_M7_DPLL_CORE, 0, 5, dpll_param_p->m7); + +// if(omap_revision() == OMAP4430_ES1_0) +// { + /* Do this only on ES1.0 */ + sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1); + sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1); + sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1); + sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1); + sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x1); + sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1); +// } + + return; +} + +void lock_core_dpll(void) +{ + /* Lock the core dpll */ + sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_LOCK); + wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY); + + return; +} + +void lock_core_dpll_shadow(void) +{ + dpll_param *dpll_param_p; + /* Lock the core dpll using freq update method */ + *(volatile int*)0x4A004120 = 10; //(CM_CLKMODE_DPLL_CORE) + + if(omap_revision() == OMAP4430_ES1_0) + dpll_param_p = &core_dpll_param_l3_190[6]; + else if(omap_revision() == OMAP4430_ES2_0) + dpll_param_p = &core_dpll_param[6]; + else if(omap_revision() == OMAP4430_ES2_1) + dpll_param_p = &core_dpll_param_ddr400[6]; + + /* CM_SHADOW_FREQ_CONFIG1: DLL_OVERRIDE = 1(hack), DLL_RESET = 1, + * DPLL_CORE_M2_DIV =1, DPLL_CORE_DPLL_EN = 0x7, FREQ_UPDATE = 1 + */ + *(volatile int*)0x4A004260 = 0x70D | (dpll_param_p->m2 << 11); + + /* Wait for Freq_Update to get cleared: CM_SHADOW_FREQ_CONFIG1 */ + while( ( (*(volatile int*)0x4A004260) & 0x1) == 0x1 ); + + /* Wait for DPLL to Lock : CM_IDLEST_DPLL_CORE */ + wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY); + //lock_core_dpll(); + + return; +} + +static void enable_all_clocks(void) +{ + volatile int regvalue = 0; + + /* Enable Ducati clocks */ + sr32(CM_DUCATI_DUCATI_CLKCTRL, 0, 32, 0x1); + sr32(CM_DUCATI_CLKSTCTRL, 0, 32, 0x2); + + wait_on_value(BIT8, BIT8, CM_DUCATI_CLKSTCTRL, LDELAY); + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DUCATI_DUCATI_CLKCTRL, LDELAY); + + /* Enable ivahd and sl2 clocks */ + sr32(IVAHD_IVAHD_CLKCTRL, 0, 32, 0x1); + sr32(IVAHD_SL2_CLKCTRL, 0, 32, 0x1); + sr32(IVAHD_CLKSTCTRL, 0, 32, 0x2); + + wait_on_value(BIT8, BIT8, IVAHD_CLKSTCTRL, LDELAY); + + /* wait for ivahd to become accessible */ + //wait_on_value(BIT18|BIT17|BIT16, 0, IVAHD_IVAHD_CLKCTRL, LDELAY); + /* wait for sl2 to become accessible */ + //wait_on_value(BIT17|BIT16, 0, IVAHD_SL2_CLKCTRL, LDELAY); + + /* Enable Tesla clocks */ + sr32(DSP_DSP_CLKCTRL, 0, 32, 0x1); + sr32(DSP_CLKSTCTRL, 0, 32, 0x2); + + wait_on_value(BIT8, BIT8, DSP_CLKSTCTRL, LDELAY); + + /* wait for tesla to become accessible */ + //wait_on_value(BIT18|BIT17|BIT16, 0, DSP_DSP_CLKCTRL, LDELAY); + + /* TODO: Some hack needed by MM: Clean this */ + #if 0 /* Doesn't work on some Zebu */ + *(volatile int*)0x4a306910 = 0x00000003; + *(volatile int*)0x550809a0 = 0x00000001; + *(volatile int*)0x55080a20 = 0x00000007; + #endif + + /* ABE clocks */ + sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x3); + sr32(CM1_ABE_AESS_CLKCTRL, 0, 32, 0x2); + //wait_on_value(BIT18|BIT17|BIT16, 0, CM1_ABE_AESS_CLKCTRL, LDELAY); + sr32(CM1_ABE_PDM_CLKCTRL, 0, 32, 0x2); + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_PDM_CLKCTRL, LDELAY); + sr32(CM1_ABE_DMIC_CLKCTRL, 0, 32, 0x2); + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_DMIC_CLKCTRL, LDELAY); + sr32(CM1_ABE_MCASP_CLKCTRL, 0, 32, 0x2); + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCASP_CLKCTRL, LDELAY); + sr32(CM1_ABE_MCBSP1_CLKCTRL, 0, 32, 0x08000002); + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP1_CLKCTRL, LDELAY); + sr32(CM1_ABE_MCBSP2_CLKCTRL, 0, 32, 0x08000002); + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP2_CLKCTRL, LDELAY); + sr32(CM1_ABE_MCBSP3_CLKCTRL, 0, 32, 0x08000002); + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP3_CLKCTRL, LDELAY); + sr32(CM1_ABE_SLIMBUS_CLKCTRL, 0, 32, 0xf02); + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_SLIMBUS_CLKCTRL, LDELAY); + sr32(CM1_ABE_TIMER5_CLKCTRL, 0, 32, 0x2); + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER5_CLKCTRL, LDELAY); + sr32(CM1_ABE_TIMER6_CLKCTRL, 0, 32, 0x2); + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER6_CLKCTRL, LDELAY); + sr32(CM1_ABE_TIMER7_CLKCTRL, 0, 32, 0x2); + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER7_CLKCTRL, LDELAY); + sr32(CM1_ABE_TIMER8_CLKCTRL, 0, 32, 0x2); + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER8_CLKCTRL, LDELAY); + sr32(CM1_ABE_WDT3_CLKCTRL, 0, 32, 0x2); + //wait_on_value(BIT17|BIT16, 0, CM1_ABE_WDT3_CLKCTRL, LDELAY); + /* Disable sleep transitions */ + sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x0); + + /* L4PER clocks */ + sr32(CM_L4PER_CLKSTCTRL, 0, 32, 0x2); + sr32(CM_L4PER_DMTIMER10_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER10_CLKCTRL, LDELAY); + sr32(CM_L4PER_DMTIMER11_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER11_CLKCTRL, LDELAY); + sr32(CM_L4PER_DMTIMER2_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER2_CLKCTRL, LDELAY); + sr32(CM_L4PER_DMTIMER3_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER3_CLKCTRL, LDELAY); + sr32(CM_L4PER_DMTIMER4_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER4_CLKCTRL, LDELAY); + sr32(CM_L4PER_DMTIMER9_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER9_CLKCTRL, LDELAY); + + /* GPIO clocks */ + sr32(CM_L4PER_GPIO2_CLKCTRL, 0 ,32, 0x1); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO2_CLKCTRL, LDELAY); + sr32(CM_L4PER_GPIO3_CLKCTRL, 0, 32, 0x1); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO3_CLKCTRL, LDELAY); + sr32(CM_L4PER_GPIO4_CLKCTRL, 0, 32, 0x1); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO4_CLKCTRL, LDELAY); + sr32(CM_L4PER_GPIO5_CLKCTRL, 0, 32, 0x1); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO5_CLKCTRL, LDELAY); + sr32(CM_L4PER_GPIO6_CLKCTRL, 0, 32, 0x1); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO6_CLKCTRL, LDELAY); + + sr32(CM_L4PER_HDQ1W_CLKCTRL, 0, 32, 0x2); + + /* I2C clocks */ + sr32(CM_L4PER_I2C1_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C1_CLKCTRL, LDELAY); + sr32(CM_L4PER_I2C2_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C2_CLKCTRL, LDELAY); + sr32(CM_L4PER_I2C3_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C3_CLKCTRL, LDELAY); + sr32(CM_L4PER_I2C4_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C4_CLKCTRL, LDELAY); + + sr32(CM_L4PER_MCBSP4_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCBSP4_CLKCTRL, LDELAY); + + /* MCSPI clocks */ + sr32(CM_L4PER_MCSPI1_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI1_CLKCTRL, LDELAY); + sr32(CM_L4PER_MCSPI2_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI2_CLKCTRL, LDELAY); + sr32(CM_L4PER_MCSPI3_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI3_CLKCTRL, LDELAY); + sr32(CM_L4PER_MCSPI4_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI4_CLKCTRL, LDELAY); + + /* MMC clocks */ + sr32(CM_L3INIT_HSMMC1_CLKCTRL, 0, 2, 0x2); + sr32(CM_L3INIT_HSMMC1_CLKCTRL, 24, 1, 0x1); + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSMMC1_CLKCTRL, LDELAY); + sr32(CM_L3INIT_HSMMC2_CLKCTRL, 0, 2, 0x2); + sr32(CM_L3INIT_HSMMC2_CLKCTRL, 24, 1, 0x1); + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSMMC2_CLKCTRL, LDELAY); + sr32(CM_L4PER_MMCSD3_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT18|BIT17|BIT16, 0, CM_L4PER_MMCSD3_CLKCTRL, LDELAY); + sr32(CM_L4PER_MMCSD4_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT18|BIT17|BIT16, 0, CM_L4PER_MMCSD4_CLKCTRL, LDELAY); + sr32(CM_L4PER_MMCSD5_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_MMCSD5_CLKCTRL, LDELAY); + + /* UART clocks */ + sr32(CM_L4PER_UART1_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART1_CLKCTRL, LDELAY); + sr32(CM_L4PER_UART2_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART2_CLKCTRL, LDELAY); + sr32(CM_L4PER_UART3_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART3_CLKCTRL, LDELAY); + sr32(CM_L4PER_UART4_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART4_CLKCTRL, LDELAY); + + /* WKUP clocks */ + sr32(CM_WKUP_GPIO1_CLKCTRL, 0, 32, 0x1); + wait_on_value(BIT17|BIT16, 0, CM_WKUP_GPIO1_CLKCTRL, LDELAY); + sr32(CM_WKUP_TIMER1_CLKCTRL, 0, 32, 0x01000002); + wait_on_value(BIT17|BIT16, 0, CM_WKUP_TIMER1_CLKCTRL, LDELAY); + + sr32(CM_WKUP_KEYBOARD_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_WKUP_KEYBOARD_CLKCTRL, LDELAY); + + sr32(CM_SDMA_CLKSTCTRL, 0, 32, 0x0); + sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x3); + sr32(CM_MEMIF_EMIF_1_CLKCTRL, 0, 32, 0x1); + wait_on_value(BIT17|BIT16, 0, CM_MEMIF_EMIF_1_CLKCTRL, LDELAY); + sr32(CM_MEMIF_EMIF_2_CLKCTRL, 0, 32, 0x1); + wait_on_value(BIT17|BIT16, 0, CM_MEMIF_EMIF_2_CLKCTRL, LDELAY); + sr32(CM_D2D_CLKSTCTRL, 0, 32, 0x3); + sr32(CM_L3_2_GPMC_CLKCTRL, 0, 32, 0x1); + wait_on_value(BIT17|BIT16, 0, CM_L3_2_GPMC_CLKCTRL, LDELAY); + sr32(CM_L3INSTR_L3_3_CLKCTRL, 0, 32, 0x1); + wait_on_value(BIT17|BIT16, 0, CM_L3INSTR_L3_3_CLKCTRL, LDELAY); + sr32(CM_L3INSTR_L3_INSTR_CLKCTRL, 0, 32, 0x1); + wait_on_value(BIT17|BIT16, 0, CM_L3INSTR_L3_INSTR_CLKCTRL, LDELAY); + sr32(CM_L3INSTR_OCP_WP1_CLKCTRL, 0, 32, 0x1); + wait_on_value(BIT17|BIT16, 0, CM_L3INSTR_OCP_WP1_CLKCTRL, LDELAY); + + /* WDT clocks */ + sr32(CM_WKUP_WDT2_CLKCTRL, 0, 32, 0x2); + wait_on_value(BIT17|BIT16, 0, CM_WKUP_WDT2_CLKCTRL, LDELAY); + + /* Enable Camera clocks */ + sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x3); + sr32(CM_CAM_ISS_CLKCTRL, 0, 32, 0x102); + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_ISS_CLKCTRL, LDELAY); + sr32(CM_CAM_FDIF_CLKCTRL, 0, 32, 0x2); + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_FDIF_CLKCTRL, LDELAY); + sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x0); + + /* Enable DSS clocks */ + /* PM_DSS_PWRSTCTRL ON State and LogicState = 1 (Retention) */ + *(volatile int*)0x4A307100 = 0x7; //DSS_PRM + sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x2); + sr32(CM_DSS_DSS_CLKCTRL, 0, 32, 0xf02); + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DSS_CLKCTRL, LDELAY); + sr32(CM_DSS_DEISS_CLKCTRL, 0, 32, 0x2); + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DEISS_CLKCTRL, LDELAY); + /* Check for DSS Clocks */ + while (((*(volatile int*)0x4A009100) & 0xF00) != 0xE00) + /* Set HW_AUTO transition mode */ + sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x3); + + /* Enable SGX clocks */ + sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x2); + sr32(CM_SGX_SGX_CLKCTRL, 0, 32, 0x2); + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_SGX_SGX_CLKCTRL, LDELAY); + /* Check for SGX FCLK and ICLK */ + while ( (*(volatile int*)0x4A009200) != 0x302 ); + //sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x0); + /* Enable hsi/unipro/usb clocks */ + sr32(CM_L3INIT_HSI_CLKCTRL, 0, 32, 0x1); + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSI_CLKCTRL, LDELAY); + sr32(CM_L3INIT_UNIPRO1_CLKCTRL, 0, 32, 0x2); + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_UNIPRO1_CLKCTRL, LDELAY); + sr32(CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, 0x2); + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBHOST_CLKCTRL, LDELAY); + sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1); + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBOTG_CLKCTRL, LDELAY); + sr32(CM_L3INIT_HSUSBTLL_CLKCTRL, 0, 32, 0x1); + //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_HSUSBTLL_CLKCTRL, LDELAY); + sr32(CM_L3INIT_FSUSB_CLKCTRL, 0, 32, 0x2); + //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_FSUSB_CLKCTRL, LDELAY); + /* enable the 32K, 48M optional clocks and enable the module */ + sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301); + //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_USBPHY_CLKCTRL, LDELAY); + return; +} + +/****************************************************************************** + * prcm_init() - inits clocks for PRCM as defined in clocks.h + * -- called from SRAM, or Flash (using temp SRAM stack). + *****************************************************************************/ +void prcm_init(void) +{ + u32 clk_index; + + /* Get the sysclk speed from cm_sys_clksel + * Set the CM_SYS_CLKSEL in case ROM code has not set + */ + __raw_writel(0x7,CM_SYS_CLKSEL); + clk_index = readl(CM_SYS_CLKSEL); + if (!clk_index) + return; /* Sys clk uninitialized */ + /* Core DPLL is locked using FREQ update method */ + /* configure_core_dpll(clk_index - 1); */ + + /* Configure all DPLL's at 100% OPP */ + configure_mpu_dpll(clk_index - 1); + configure_iva_dpll(clk_index - 1); + configure_per_dpll(clk_index - 1); + configure_abe_dpll(clk_index - 1); + configure_usb_dpll(clk_index - 1); + +#ifdef CONFIG_OMAP4_SDC + /* Enable all clocks */ + enable_all_clocks(); +#endif + + return; +} diff --git a/board/omap4430panda/config.mk b/board/omap4430panda/config.mk new file mode 100644 index 0000000..01173eb --- /dev/null +++ b/board/omap4430panda/config.mk @@ -0,0 +1,21 @@ +# +# (C) Copyright 2006-2009 +# Texas Instruments, <www.ti.com> +# +# SDP4430 board uses ARM-CortexA9 cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +TEXT_BASE = 0x40304350 + + +# Handy to get symbols to debug ROM version. +#TEXT_BASE = 0x0 +#TEXT_BASE = 0x08000000 +#TEXT_BASE = 0x04000000 diff --git a/board/omap4430panda/omap4430panda.c b/board/omap4430panda/omap4430panda.c new file mode 100644 index 0000000..5695733 --- /dev/null +++ b/board/omap4430panda/omap4430panda.c @@ -0,0 +1,1235 @@ +/* + * (C) Copyright 2004-2009 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/arch/cpu.h> +#include <asm/io.h> +#include <asm/arch/bits.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/sys_info.h> +#include <asm/arch/clocks.h> +#include <asm/arch/mem.h> +#include <i2c.h> +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) +#include <linux/mtd/nand_legacy.h> +#endif + +/* EMIF and DMM registers */ +#define EMIF1_BASE 0x4c000000 +#define EMIF2_BASE 0x4d000000 +#define DMM_BASE 0x4e000000 +/* EMIF */ +#define EMIF_MOD_ID_REV 0x0000 +#define EMIF_STATUS 0x0004 +#define EMIF_SDRAM_CONFIG 0x0008 +#define EMIF_LPDDR2_NVM_CONFIG 0x000C +#define EMIF_SDRAM_REF_CTRL 0x0010 +#define EMIF_SDRAM_REF_CTRL_SHDW 0x0014 +#define EMIF_SDRAM_TIM_1 0x0018 +#define EMIF_SDRAM_TIM_1_SHDW 0x001C +#define EMIF_SDRAM_TIM_2 0x0020 +#define EMIF_SDRAM_TIM_2_SHDW 0x0024 +#define EMIF_SDRAM_TIM_3 0x0028 +#define EMIF_SDRAM_TIM_3_SHDW 0x002C +#define EMIF_LPDDR2_NVM_TIM 0x0030 +#define EMIF_LPDDR2_NVM_TIM_SHDW 0x0034 +#define EMIF_PWR_MGMT_CTRL 0x0038 +#define EMIF_PWR_MGMT_CTRL_SHDW 0x003C +#define EMIF_LPDDR2_MODE_REG_DATA 0x0040 +#define EMIF_LPDDR2_MODE_REG_CFG 0x0050 +#define EMIF_L3_CONFIG 0x0054 +#define EMIF_L3_CFG_VAL_1 0x0058 +#define EMIF_L3_CFG_VAL_2 0x005C +#define IODFT_TLGC 0x0060 +#define EMIF_PERF_CNT_1 0x0080 +#define EMIF_PERF_CNT_2 0x0084 +#define EMIF_PERF_CNT_CFG 0x0088 +#define EMIF_PERF_CNT_SEL 0x008C +#define EMIF_PERF_CNT_TIM 0x0090 +#define EMIF_READ_IDLE_CTRL 0x0098 +#define EMIF_READ_IDLE_CTRL_SHDW 0x009c +#define EMIF_ZQ_CONFIG 0x00C8 +#define EMIF_DDR_PHY_CTRL_1 0x00E4 +#define EMIF_DDR_PHY_CTRL_1_SHDW 0x00E8 +#define EMIF_DDR_PHY_CTRL_2 0x00EC + +#define DMM_LISA_MAP_0 0x0040 +#define DMM_LISA_MAP_1 0x0044 +#define DMM_LISA_MAP_2 0x0048 +#define DMM_LISA_MAP_3 0x004C + +#define MR0_ADDR 0 +#define MR1_ADDR 1 +#define MR2_ADDR 2 +#define MR4_ADDR 4 +#define MR10_ADDR 10 +#define MR16_ADDR 16 +#define REF_EN 0x40000000 +/* defines for MR1 */ +#define MR1_BL4 2 +#define MR1_BL8 3 +#define MR1_BL16 4 + +#define MR1_BT_SEQ 0 +#define BT_INT 1 + +#define MR1_WC 0 +#define MR1_NWC 1 + +#define MR1_NWR3 1 +#define MR1_NWR4 2 +#define MR1_NWR5 3 +#define MR1_NWR6 4 +#define MR1_NWR7 5 +#define MR1_NWR8 6 + +#define MR1_VALUE (MR1_NWR3 << 5) | (MR1_WC << 4) | (MR1_BT_SEQ << 3) \ + | (MR1_BL8 << 0) + +/* defines for MR2 */ +#define MR2_RL3_WL1 1 +#define MR2_RL4_WL2 2 +#define MR2_RL5_WL2 3 +#define MR2_RL6_WL3 4 + +/* defines for MR10 */ +#define MR10_ZQINIT 0xFF +#define MR10_ZQRESET 0xC3 +#define MR10_ZQCL 0xAB +#define MR10_ZQCS 0x56 + + +/* TODO: FREQ update method is not working so shadow registers programming + * is just for same of completeness. This would be safer if auto + * trasnitions are working + */ +#define FREQ_UPDATE_EMIF +/* EMIF Needs to be configured@19.2 MHz and shadow registers + * should be programmed for new OPP. + */ +/* Elpida 2x2Gbit */ +#define SDRAM_CONFIG_INIT 0x80800EB1 +#define DDR_PHY_CTRL_1_INIT 0x849FFFF5 +#define READ_IDLE_CTRL 0x000501FF +#define PWR_MGMT_CTRL 0x4000000f +#define PWR_MGMT_CTRL_OPP100 0x4000000f +#define ZQ_CONFIG 0x500b3215 + +#define CS1_MR(mr) ((mr) | 0x80000000) +struct ddr_regs{ + u32 tim1; + u32 tim2; + u32 tim3; + u32 phy_ctrl_1; + u32 ref_ctrl; + u32 config_init; + u32 config_final; + u32 zq_config; + u8 mr1; + u8 mr2; +}; +const struct ddr_regs ddr_regs_380_mhz = { + .tim1 = 0x10cb061a, + .tim2 = 0x20350d52, + .tim3 = 0x00b1431f, + .phy_ctrl_1 = 0x849FF408, + .ref_ctrl = 0x000005ca, + .config_init = 0x80000eb1, + .config_final = 0x80001ab1, + .zq_config = 0x500b3215, + .mr1 = 0x83, + .mr2 = 0x4 +}; + +/* + * Unused timings - but we may need them later + * Keep them commented + */ +#if 0 +const struct ddr_regs ddr_regs_400_mhz = { + .tim1 = 0x10eb065a, + .tim2 = 0x20370dd2, + .tim3 = 0x00b1c33f, + .phy_ctrl_1 = 0x849FF408, + .ref_ctrl = 0x00000618, + .config_init = 0x80000eb1, + .config_final = 0x80001ab1, + .zq_config = 0x500b3215, + .mr1 = 0x83, + .mr2 = 0x4 +}; + +const struct ddr_regs ddr_regs_200_mhz = { + .tim1 = 0x08648309, + .tim2 = 0x101b06ca, + .tim3 = 0x0048a19f, + .phy_ctrl_1 = 0x849FF405, + .ref_ctrl = 0x0000030c, + .config_init = 0x80000eb1, + .config_final = 0x80000eb1, + .zq_config = 0x500b3215, + .mr1 = 0x23, + .mr2 = 0x1 +}; +#endif + +const struct ddr_regs ddr_regs_200_mhz_2cs = { + .tim1 = 0x08648309, + .tim2 = 0x101b06ca, + .tim3 = 0x0048a19f, + .phy_ctrl_1 = 0x849FF405, + .ref_ctrl = 0x0000030c, + .config_init = 0x80000eb9, + .config_final = 0x80000eb9, + .zq_config = 0xD00b3215, + .mr1 = 0x23, + .mr2 = 0x1 +}; + +const struct ddr_regs ddr_regs_400_mhz_2cs = { + /* tRRD changed from 10ns to 12.5ns because of the tFAW requirement*/ + .tim1 = 0x10eb0662, + .tim2 = 0x20370dd2, + .tim3 = 0x00b1c33f, + .phy_ctrl_1 = 0x849FF408, + .ref_ctrl = 0x00000618, + .config_init = 0x80000eb9, + .config_final = 0x80001ab9, + .zq_config = 0xD00b3215, + .mr1 = 0x83, + .mr2 = 0x4 +}; + +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b" : "=r" (loops) : "0"(loops)); +} + + +void big_delay(unsigned int count) +{ + int i; + for (i=0; i<count; i++) + delay(1); +} + +/* TODO: FREQ update method is not working so shadow registers programming + * is just for same of completeness. This would be safer if auto + * trasnitions are working + */ +static int emif_config(unsigned int base) +{ + unsigned int reg_value, rev; + const struct ddr_regs *ddr_regs; + rev = omap_revision(); + + if(rev == OMAP4430_ES1_0) + ddr_regs = &ddr_regs_380_mhz; + else if (rev == OMAP4430_ES2_0) + ddr_regs = &ddr_regs_200_mhz_2cs; + else if (rev == OMAP4430_ES2_1) + ddr_regs = &ddr_regs_400_mhz_2cs; + /* + * set SDRAM CONFIG register + * EMIF_SDRAM_CONFIG[31:29] REG_SDRAM_TYPE = 4 for LPDDR2-S4 + * EMIF_SDRAM_CONFIG[28:27] REG_IBANK_POS = 0 + * EMIF_SDRAM_CONFIG[13:10] REG_CL = 3 + * EMIF_SDRAM_CONFIG[6:4] REG_IBANK = 3 - 8 banks + * EMIF_SDRAM_CONFIG[3] REG_EBANK = 0 - CS0 + * EMIF_SDRAM_CONFIG[2:0] REG_PAGESIZE = 2 - 512- 9 column + * JDEC specs - S4-2Gb --8 banks -- R0-R13, C0-c8 + */ + *(volatile int*)(base + EMIF_LPDDR2_NVM_CONFIG) &= 0xBFFFFFFF; + *(volatile int*)(base + EMIF_SDRAM_CONFIG) = ddr_regs->config_init; + + /* PHY control values */ + *(volatile int*)(base + EMIF_DDR_PHY_CTRL_1) = DDR_PHY_CTRL_1_INIT; + *(volatile int*)(base + EMIF_DDR_PHY_CTRL_1_SHDW)= ddr_regs->phy_ctrl_1; + + /* + * EMIF_READ_IDLE_CTRL + */ + *(volatile int*)(base + EMIF_READ_IDLE_CTRL) = READ_IDLE_CTRL; + *(volatile int*)(base + EMIF_READ_IDLE_CTRL_SHDW) = READ_IDLE_CTRL; + + /* + * EMIF_SDRAM_TIM_1 + */ + *(volatile int*)(base + EMIF_SDRAM_TIM_1) = ddr_regs->tim1; + *(volatile int*)(base + EMIF_SDRAM_TIM_1_SHDW) = ddr_regs->tim1; + + /* + * EMIF_SDRAM_TIM_2 + */ + *(volatile int*)(base + EMIF_SDRAM_TIM_2) = ddr_regs->tim2; + *(volatile int*)(base + EMIF_SDRAM_TIM_2_SHDW) = ddr_regs->tim2; + + /* + * EMIF_SDRAM_TIM_3 + */ + *(volatile int*)(base + EMIF_SDRAM_TIM_3) = ddr_regs->tim3; + *(volatile int*)(base + EMIF_SDRAM_TIM_3_SHDW) = ddr_regs->tim3; + + *(volatile int*)(base + EMIF_ZQ_CONFIG) = ddr_regs->zq_config; + /* + * EMIF_PWR_MGMT_CTRL + */ + //*(volatile int*)(base + EMIF_PWR_MGMT_CTRL) = PWR_MGMT_CTRL; + //*(volatile int*)(base + EMIF_PWR_MGMT_CTRL_SHDW) = PWR_MGMT_CTRL_OPP100; + /* + * poll MR0 register (DAI bit) + * REG_CS[31] = 0 -- Mode register command to CS0 + * REG_REFRESH_EN[30] = 1 -- Refresh enable after MRW + * REG_ADDRESS[7:0] = 00 -- Refresh enable after MRW + */ + + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = MR0_ADDR; + do { + reg_value = *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA); + } while ((reg_value & 0x1) != 0); + + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = CS1_MR(MR0_ADDR); + do { + reg_value = *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA); + } while ((reg_value & 0x1) != 0); + + + /* set MR10 register */ + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR10_ADDR; + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = MR10_ZQINIT; + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = CS1_MR(MR10_ADDR); + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = MR10_ZQINIT; + + /* wait for tZQINIT=1us */ + delay(10); + + /* set MR1 register */ + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR1_ADDR; + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = ddr_regs->mr1; + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = CS1_MR(MR1_ADDR); + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = ddr_regs->mr1; + + + /* set MR2 register RL=6 for OPP100 */ + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR2_ADDR; + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = ddr_regs->mr2; + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = CS1_MR(MR2_ADDR); + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = ddr_regs->mr2; + + /* Set SDRAM CONFIG register again here with final RL-WL value */ + *(volatile int*)(base + EMIF_SDRAM_CONFIG) = ddr_regs->config_final; + *(volatile int*)(base + EMIF_DDR_PHY_CTRL_1) = ddr_regs->phy_ctrl_1; + + /* + * EMIF_SDRAM_REF_CTRL + * refresh rate = DDR_CLK / reg_refresh_rate + * 3.9 uS = (400MHz) / reg_refresh_rate + */ + *(volatile int*)(base + EMIF_SDRAM_REF_CTRL) = ddr_regs->ref_ctrl; + *(volatile int*)(base + EMIF_SDRAM_REF_CTRL_SHDW) = ddr_regs->ref_ctrl; + + /* set MR16 register */ + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR16_ADDR | REF_EN; + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = 0; + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = + CS1_MR(MR16_ADDR | REF_EN); + *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = 0; + /* LPDDR2 init complete */ + +} +/***************************************** + * Routine: ddr_init + * Description: Configure DDR + * EMIF1 -- CS0 -- DDR1 (256 MB) + * EMIF2 -- CS0 -- DDR2 (256 MB) + *****************************************/ +static void ddr_init(void) +{ + unsigned int base_addr, rev; + rev = omap_revision(); + + if (rev == OMAP4430_ES1_0) + { + /* Configurte the Control Module DDRIO device */ + __raw_writel(0x1c1c1c1c, 0x4A100638); + __raw_writel(0x1c1c1c1c, 0x4A10063c); + __raw_writel(0x1c1c1c1c, 0x4A100640); + __raw_writel(0x1c1c1c1c, 0x4A100648); + __raw_writel(0x1c1c1c1c, 0x4A10064c); + __raw_writel(0x1c1c1c1c, 0x4A100650); + /* LPDDR2IO set to NMOS PTV */ + __raw_writel(0x00ffc000, 0x4A100704); + } else if (rev == OMAP4430_ES2_0) { + __raw_writel(0x9e9e9e9e, 0x4A100638); + __raw_writel(0x9e9e9e9e, 0x4A10063c); + __raw_writel(0x9e9e9e9e, 0x4A100640); + __raw_writel(0x9e9e9e9e, 0x4A100648); + __raw_writel(0x9e9e9e9e, 0x4A10064c); + __raw_writel(0x9e9e9e9e, 0x4A100650); + /* LPDDR2IO set to NMOS PTV */ + __raw_writel(0x00ffc000, 0x4A100704); + } + + /* + * DMM Configuration + */ + + /* Both EMIFs 128 byte interleaved*/ + if (rev == OMAP4430_ES1_0) + *(volatile int*)(DMM_BASE + DMM_LISA_MAP_0) = 0x80540300; + else + *(volatile int*)(DMM_BASE + DMM_LISA_MAP_0) = 0x80640300; + + /* EMIF2 only at 0x90000000 */ + //*(volatile int*)(DMM_BASE + DMM_LISA_MAP_1) = 0x90400200; + + *(volatile int*)(DMM_BASE + DMM_LISA_MAP_2) = 0x00000000; + *(volatile int*)(DMM_BASE + DMM_LISA_MAP_3) = 0xFF020100; + + /* DDR needs to be initialised @ 19.2 MHz + * So put core DPLL in bypass mode + * Configure the Core DPLL but don't lock it + */ + configure_core_dpll_no_lock(); + + /* No IDLE: BUG in SDC */ + //sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2); + //while(((*(volatile int*)CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700); + *(volatile int*)(EMIF1_BASE + EMIF_PWR_MGMT_CTRL) = 0x0; + *(volatile int*)(EMIF2_BASE + EMIF_PWR_MGMT_CTRL) = 0x0; + + base_addr = EMIF1_BASE; + emif_config(base_addr); + + /* Configure EMIF24D */ + base_addr = EMIF2_BASE; + emif_config(base_addr); + /* Lock Core using shadow CM_SHADOW_FREQ_CONFIG1 */ + lock_core_dpll_shadow(); + /* TODO: SDC needs few hacks to get DDR freq update working */ + + /* Set DLL_OVERRIDE = 0 */ + *(volatile int*)CM_DLL_CTRL = 0x0; + + delay(200); + + /* Check for DDR PHY ready for EMIF1 & EMIF2 */ + while((((*(volatile int*)(EMIF1_BASE + EMIF_STATUS))&(0x04)) != 0x04) \ + || (((*(volatile int*)(EMIF2_BASE + EMIF_STATUS))&(0x04)) != 0x04)); + + /* Reprogram the DDR PYHY Control register */ + /* PHY control values */ + + sr32(CM_MEMIF_EMIF_1_CLKCTRL, 0, 32, 0x1); + sr32(CM_MEMIF_EMIF_2_CLKCTRL, 0, 32, 0x1); + + /* Put the Core Subsystem PD to ON State */ + + /* No IDLE: BUG in SDC */ + //sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2); + //while(((*(volatile int*)CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700); + *(volatile int*)(EMIF1_BASE + EMIF_PWR_MGMT_CTRL) = 0x80000000; + *(volatile int*)(EMIF2_BASE + EMIF_PWR_MGMT_CTRL) = 0x80000000; + + /* SYSTEM BUG: + * In n a specific situation, the OCP interface between the DMM and + * EMIF may hang. + * 1. A TILER port is used to perform 2D burst writes of + * width 1 and height 8 + * 2. ELLAn port is used to perform reads + * 3. All accesses are routed to the same EMIF controller + * + * Work around to avoid this issue REG_SYS_THRESH_MAX value should + * be kept higher than default 0x7. As per recommondation 0x0A will + * be used for better performance with REG_LL_THRESH_MAX = 0x00 + */ + if (rev == OMAP4430_ES1_0) { + *(volatile int*)(EMIF1_BASE + EMIF_L3_CONFIG) = 0x0A0000FF; + *(volatile int*)(EMIF2_BASE + EMIF_L3_CONFIG) = 0x0A0000FF; + } + + /* + * DMM : DMM_LISA_MAP_0(Section_0) + * [31:24] SYS_ADDR 0x80 + * [22:20] SYS_SIZE 0x7 - 2Gb + * [19:18] SDRC_INTLDMM 0x1 - 128 byte + * [17:16] SDRC_ADDRSPC 0x0 + * [9:8] SDRC_MAP 0x3 + * [7:0] SDRC_ADDR 0X0 + */ + reset_phy(EMIF1_BASE); + reset_phy(EMIF2_BASE); + + *((volatile int *)0x80000000) = 0; + *((volatile int *)0x80000080) = 0; + //*((volatile int *)0x90000000) = 0; +} +/***************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************/ +int board_init(void) +{ + return 0; +} + +/************************************************************* + * Routine: get_mem_type(void) - returns the kind of memory connected + * to GPMC that we are trying to boot form. Uses SYS BOOT settings. + *************************************************************/ +u32 get_mem_type(void) +{ + /* no nand, so return GPMC_NONE */ + return GPMC_NONE; +} + +/***************************************** + * Routine: secure_unlock + * Description: Setup security registers for access + * (GP Device only) + *****************************************/ +void secure_unlock_mem(void) +{ + /* Permission values for registers -Full fledged permissions to all */ + #define UNLOCK_1 0xFFFFFFFF + #define UNLOCK_2 0x00000000 + #define UNLOCK_3 0x0000FFFF + + /* Protection Module Register Target APE (PM_RT)*/ + __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1); + __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0); + __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1); + + __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0); + __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2); + + /* IVA Changes */ + __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0); + __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0); + + __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */ +} + +/********************************************************** + * Routine: try_unlock_sram() + * Description: If chip is GP/EMU(special) type, unlock the SRAM for + * general use. + ***********************************************************/ +void try_unlock_memory(void) +{ + int mode; + + /* if GP device unlock device SRAM for general use */ + /* secure code breaks for Secure/Emulation device - HS/E/T*/ + return; +} + + +#if defined(CONFIG_MPU_600) || defined(CONFIG_MPU_1000) +static scale_vcores(void) +{ + unsigned int rev = omap_revision(); + /* For VC bypass only VCOREx_CGF_FORCE is necessary and + * VCOREx_CFG_VOLTAGE changes can be discarded + */ + /* PRM_VC_CFG_I2C_MODE */ + *(volatile int*)(0x4A307BA8) = 0x0; + /* PRM_VC_CFG_I2C_CLK */ + *(volatile int*)(0x4A307BAC) = 0x6026; + + /* set VCORE1 force VSEL */ + /* PRM_VC_VAL_BYPASS) */ + if(rev == OMAP4430_ES1_0) + *(volatile int*)(0x4A307BA0) = 0x3B5512; + else + *(volatile int*)(0x4A307BA0) = 0x3A5512; + + *(volatile int*)(0x4A307BA0) |= 0x1000000; + while((*(volatile int*)(0x4A307BA0)) & 0x1000000); + + /* PRM_IRQSTATUS_MPU */ + *(volatile int*)(0x4A306010) = *(volatile int*)(0x4A306010); + + + /* FIXME: set VCORE2 force VSEL, Check the reset value */ + /* PRM_VC_VAL_BYPASS) */ + if(rev == OMAP4430_ES1_0) + *(volatile int*)(0x4A307BA0) = 0x315B12; + else + *(volatile int*)(0x4A307BA0) = 0x295B12; + *(volatile int*)(0x4A307BA0) |= 0x1000000; + while((*(volatile int*)(0x4A307BA0)) & 0x1000000); + + /* PRM_IRQSTATUS_MPU */ + *(volatile int*)(0x4A306010) = *(volatile int*)(0x4A306010); + + /*/set VCORE3 force VSEL */ + /* PRM_VC_VAL_BYPASS */ + if(rev == OMAP4430_ES1_0) + *(volatile int*)(0x4A307BA0) = 0x316112; + else if (rev == OMAP4430_ES2_0) + *(volatile int*)(0x4A307BA0) = 0x296112; + else if (rev == OMAP4430_ES2_1) + *(volatile int*)(0x4A307BA0) = 0x2A6112; + *(volatile int*)(0x4A307BA0) |= 0x1000000; + while((*(volatile int*)(0x4A307BA0)) & 0x1000000); + + /* PRM_IRQSTATUS_MPU */ + *(volatile int*)(0x4A306010) = *(volatile int*)(0x4A306010); + +} +#endif + +/********************************************************** + * Routine: s_init + * Description: Does early system init of muxing and clocks. + * - Called path is with SRAM stack. + **********************************************************/ + +void s_init(void) +{ + unsigned int rev = omap_revision(); + + set_muxconf_regs(); + delay(100); + + /* Writing to AuxCR in U-boot using SMI for GP/EMU DEV */ + /* Currently SMI in Kernel on ES2 devices seems to have an isse + * Once that is resolved, we can postpone this config to kernel + */ + //setup_auxcr(get_device_type(), external_boot); + + ddr_init(); + +/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */ +#if defined(CONFIG_MPU_600) || defined(CONFIG_MPU_1000) + scale_vcores(); +#endif + prcm_init(); + + if(rev != OMAP4430_ES1_0) { + if (__raw_readl(0x4805D138) & (1<<22)) { + sr32(0x4A30a31C, 8, 1, 0x1); /* enable software ioreq */ + sr32(0x4A30a31C, 1, 2, 0x0); /* set for sys_clk (38.4MHz) */ + sr32(0x4A30a31C, 16, 4, 0x1); /* set divisor to 2 */ + sr32(0x4A30a110, 0, 1, 0x1); /* set the clock source to active */ + sr32(0x4A30a110, 2, 2, 0x3); /* enable clocks */ + } + else { + sr32(0x4A30a314, 8, 1, 0x1); /* enable software ioreq */ + sr32(0x4A30a314, 1, 2, 0x2); /* set for PER_DPLL */ + sr32(0x4A30a314, 16, 4, 0xf); /* set divisor to 16 */ + sr32(0x4A30a110, 0, 1, 0x1); /* set the clock source to active */ + sr32(0x4A30a110, 2, 2, 0x3); /* enable clocks */ + } + } + +} + +/******************************************************* + * Routine: misc_init_r + * Description: Init ethernet (done here so udelay works) + ********************************************************/ +int misc_init_r(void) +{ + return 0; +} + +/****************************************************** + * Routine: wait_for_command_complete + * Description: Wait for posting to finish on watchdog + ******************************************************/ +void wait_for_command_complete(unsigned int wd_base) +{ + int pending = 1; + do { + pending = __raw_readl(wd_base + WWPS); + } while (pending); +} + +/******************************************************************* + * Routine:ether_init + * Description: take the Ethernet controller out of reset and wait + * for the EEPROM load to complete. + ******************************************************************/ + +/********************************************** + * Routine: dram_init + * Description: sets uboots idea of sdram size + **********************************************/ +int dram_init(void) +{ + return 0; +} + +#define OMAP44XX_WKUP_CTRL_BASE 0x4A31E000 +#if 1 +#define M0_SAFE M0 +#define M1_SAFE M1 +#define M2_SAFE M2 +#define M4_SAFE M4 +#define M7_SAFE M7 +#define M3_SAFE M3 +#define M5_SAFE M5 +#define M6_SAFE M6 +#else +#define M0_SAFE M7 +#define M1_SAFE M7 +#define M2_SAFE M7 +#define M4_SAFE M7 +#define M7_SAFE M7 +#define M3_SAFE M7 +#define M5_SAFE M7 +#define M6_SAFE M7 +#endif +#define MV(OFFSET, VALUE)\ + __raw_writew((VALUE), OMAP44XX_CTRL_BASE + (OFFSET)); +#define MV1(OFFSET, VALUE)\ + __raw_writew((VALUE), OMAP44XX_WKUP_CTRL_BASE + (OFFSET)); + +#define CP(x) (CONTROL_PADCONF_##x) +#define WK(x) (CONTROL_WKUP_##x) +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ + +#define MUX_DEFAULT_OMAP4() \ + MV(CP(GPMC_AD0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat0 */ \ + MV(CP(GPMC_AD1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat1 */ \ + MV(CP(GPMC_AD2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat2 */ \ + MV(CP(GPMC_AD3) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat3 */ \ + MV(CP(GPMC_AD4) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat4 */ \ + MV(CP(GPMC_AD5) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat5 */ \ + MV(CP(GPMC_AD6) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat6 */ \ + MV(CP(GPMC_AD7) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat7 */ \ + MV(CP(GPMC_AD8) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpio_32 */ \ + MV(CP(GPMC_AD9) , ( PTU | IEN | M3)) /* gpio_33 */ \ + MV(CP(GPMC_AD10) , ( PTU | IEN | M3)) /* gpio_34 */ \ + MV(CP(GPMC_AD11) , ( PTU | IEN | M3)) /* gpio_35 */ \ + MV(CP(GPMC_AD12) , ( PTU | IEN | M3)) /* gpio_36 */ \ + MV(CP(GPMC_AD13) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_37 */ \ + MV(CP(GPMC_AD14) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_38 */ \ + MV(CP(GPMC_AD15) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_39 */ \ + MV(CP(GPMC_A16) , ( M3)) /* gpio_40 */ \ + MV(CP(GPMC_A17) , ( PTD | M3)) /* gpio_41 */ \ + MV(CP(GPMC_A18) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row6 */ \ + MV(CP(GPMC_A19) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row7 */ \ + MV(CP(GPMC_A20) , ( IEN | M3)) /* gpio_44 */ \ + MV(CP(GPMC_A21) , ( M3)) /* gpio_45 */ \ + MV(CP(GPMC_A22) , ( M3)) /* gpio_46 */ \ + MV(CP(GPMC_A23) , ( OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col7 */ \ + MV(CP(GPMC_A24) , ( PTD | M3)) /* gpio_48 */ \ + MV(CP(GPMC_A25) , ( PTD | M3)) /* gpio_49 */ \ + MV(CP(GPMC_NCS0) , ( M3)) /* gpio_50 */ \ + MV(CP(GPMC_NCS1) , ( IEN | M3)) /* gpio_51 */ \ + MV(CP(GPMC_NCS2) , ( IEN | M3)) /* gpio_52 */ \ + MV(CP(GPMC_NCS3) , ( IEN | M3)) /* gpio_53 */ \ + MV(CP(GPMC_NWP) , ( M3)) /* gpio_54 */ \ + MV(CP(GPMC_CLK) , ( PTD | M3)) /* gpio_55 */ \ + MV(CP(GPMC_NADV_ALE) , ( M3)) /* gpio_56 */ \ + MV(CP(GPMC_NOE) , ( PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)) /* sdmmc2_clk */ \ + MV(CP(GPMC_NWE) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_cmd */ \ + MV(CP(GPMC_NBE0_CLE) , ( M3)) /* gpio_59 */ \ + MV(CP(GPMC_NBE1) , ( PTD | M3)) /* gpio_60 */ \ + MV(CP(GPMC_WAIT0) , ( PTU | IEN | M3)) /* gpio_61 */ \ + MV(CP(GPMC_WAIT1), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_62 */ \ + MV(CP(C2C_DATA11) , ( PTD | M3)) /* gpio_100 */ \ + MV(CP(C2C_DATA12) , ( PTD | IEN | M3)) /* gpio_101 */ \ + MV(CP(C2C_DATA13) , ( PTD | M3)) /* gpio_102 */ \ + MV(CP(C2C_DATA14) , ( M1)) /* dsi2_te0 */ \ + MV(CP(C2C_DATA15) , ( PTD | M3)) /* gpio_104 */ \ + MV(CP(HDMI_HPD) , ( M0)) /* hdmi_hpd */ \ + MV(CP(HDMI_CEC) , ( M0)) /* hdmi_cec */ \ + MV(CP(HDMI_DDC_SCL) , ( PTU | M0)) /* hdmi_ddc_scl */ \ + MV(CP(HDMI_DDC_SDA) , ( PTU | IEN | M0)) /* hdmi_ddc_sda */ \ + MV(CP(CSI21_DX0) , ( IEN | M0)) /* csi21_dx0 */ \ + MV(CP(CSI21_DY0) , ( IEN | M0)) /* csi21_dy0 */ \ + MV(CP(CSI21_DX1) , ( IEN | M0)) /* csi21_dx1 */ \ + MV(CP(CSI21_DY1) , ( IEN | M0)) /* csi21_dy1 */ \ + MV(CP(CSI21_DX2) , ( IEN | M0)) /* csi21_dx2 */ \ + MV(CP(CSI21_DY2) , ( IEN | M0)) /* csi21_dy2 */ \ + MV(CP(CSI21_DX3) , ( PTD | M7)) /* csi21_dx3 */ \ + MV(CP(CSI21_DY3) , ( PTD | M7)) /* csi21_dy3 */ \ + MV(CP(CSI21_DX4) , ( PTD | OFF_EN | OFF_PD | OFF_IN | M7)) /* csi21_dx4 */ \ + MV(CP(CSI21_DY4) , ( PTD | OFF_EN | OFF_PD | OFF_IN | M7)) /* csi21_dy4 */ \ + MV(CP(CSI22_DX0) , ( IEN | M0)) /* csi22_dx0 */ \ + MV(CP(CSI22_DY0) , ( IEN | M0)) /* csi22_dy0 */ \ + MV(CP(CSI22_DX1) , ( IEN | M0)) /* csi22_dx1 */ \ + MV(CP(CSI22_DY1) , ( IEN | M0)) /* csi22_dy1 */ \ + MV(CP(CAM_SHUTTER) , ( OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* cam_shutter */ \ + MV(CP(CAM_STROBE) , ( OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* cam_strobe */ \ + MV(CP(CAM_GLOBALRESET) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_83 */ \ + MV(CP(USBB1_ULPITLL_CLK) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_clk */ \ + MV(CP(USBB1_ULPITLL_STP) , ( OFF_EN | OFF_OUT_PTD | M4)) /* usbb1_ulpiphy_stp */ \ + MV(CP(USBB1_ULPITLL_DIR) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dir */ \ + MV(CP(USBB1_ULPITLL_NXT) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_nxt */ \ + MV(CP(USBB1_ULPITLL_DAT0) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat0 */ \ + MV(CP(USBB1_ULPITLL_DAT1) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat1 */ \ + MV(CP(USBB1_ULPITLL_DAT2) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat2 */ \ + MV(CP(USBB1_ULPITLL_DAT3) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat3 */ \ + MV(CP(USBB1_ULPITLL_DAT4) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat4 */ \ + MV(CP(USBB1_ULPITLL_DAT5) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat5 */ \ + MV(CP(USBB1_ULPITLL_DAT6) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat6 */ \ + MV(CP(USBB1_ULPITLL_DAT7) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat7 */ \ + MV(CP(USBB1_HSIC_DATA) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usbb1_hsic_data */ \ + MV(CP(USBB1_HSIC_STROBE) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usbb1_hsic_strobe */ \ + MV(CP(USBC1_ICUSB_DP) , ( IEN | M0)) /* usbc1_icusb_dp */ \ + MV(CP(USBC1_ICUSB_DM) , ( IEN | M0)) /* usbc1_icusb_dm */ \ + MV(CP(SDMMC1_CLK) , ( PTU | OFF_EN | OFF_OUT_PTD | M0)) /* sdmmc1_clk */ \ + MV(CP(SDMMC1_CMD) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_cmd */ \ + MV(CP(SDMMC1_DAT0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat0 */ \ + MV(CP(SDMMC1_DAT1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat1 */ \ + MV(CP(SDMMC1_DAT2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat2 */ \ + MV(CP(SDMMC1_DAT3) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat3 */ \ + MV(CP(SDMMC1_DAT4) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat4 */ \ + MV(CP(SDMMC1_DAT5) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat5 */ \ + MV(CP(SDMMC1_DAT6) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat6 */ \ + MV(CP(SDMMC1_DAT7) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat7 */ \ + MV(CP(ABE_MCBSP2_CLKX) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp2_clkx */ \ + MV(CP(ABE_MCBSP2_DR) , ( IEN | OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp2_dr */ \ + MV(CP(ABE_MCBSP2_DX) , ( OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp2_dx */ \ + MV(CP(ABE_MCBSP2_FSX) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp2_fsx */ \ + MV(CP(ABE_MCBSP1_CLKX) , ( IEN | M1)) /* abe_slimbus1_clock */ \ + MV(CP(ABE_MCBSP1_DR) , ( IEN | M1)) /* abe_slimbus1_data */ \ + MV(CP(ABE_MCBSP1_DX) , ( OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp1_dx */ \ + MV(CP(ABE_MCBSP1_FSX) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp1_fsx */ \ + MV(CP(ABE_PDM_UL_DATA) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_pdm_ul_data */ \ + MV(CP(ABE_PDM_DL_DATA) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_pdm_dl_data */ \ + MV(CP(ABE_PDM_FRAME) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_pdm_frame */ \ + MV(CP(ABE_PDM_LB_CLK) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_pdm_lb_clk */ \ + MV(CP(ABE_CLKS) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_clks */ \ + MV(CP(ABE_DMIC_CLK1) , ( M0)) /* abe_dmic_clk1 */ \ + MV(CP(ABE_DMIC_DIN1) , ( IEN | M0)) /* abe_dmic_din1 */ \ + MV(CP(ABE_DMIC_DIN2) , ( IEN | M0)) /* abe_dmic_din2 */ \ + MV(CP(ABE_DMIC_DIN3) , ( IEN | M0)) /* abe_dmic_din3 */ \ + MV(CP(UART2_CTS) , ( PTU | IEN | M0)) /* uart2_cts */ \ + MV(CP(UART2_RTS) , ( M0)) /* uart2_rts */ \ + MV(CP(UART2_RX) , ( PTU | IEN | M0)) /* uart2_rx */ \ + MV(CP(UART2_TX) , ( M0)) /* uart2_tx */ \ + MV(CP(HDQ_SIO) , ( M3)) /* gpio_127 */ \ + MV(CP(I2C1_SCL) , ( PTU | IEN | M0)) /* i2c1_scl */ \ + MV(CP(I2C1_SDA) , ( PTU | IEN | M0)) /* i2c1_sda */ \ + MV(CP(I2C2_SCL) , ( PTU | IEN | M0)) /* i2c2_scl */ \ + MV(CP(I2C2_SDA) , ( PTU | IEN | M0)) /* i2c2_sda */ \ + MV(CP(I2C3_SCL) , ( PTU | IEN | M0)) /* i2c3_scl */ \ + MV(CP(I2C3_SDA) , ( PTU | IEN | M0)) /* i2c3_sda */ \ + MV(CP(I2C4_SCL) , ( PTU | IEN | M0)) /* i2c4_scl */ \ + MV(CP(I2C4_SDA) , ( PTU | IEN | M0)) /* i2c4_sda */ \ + MV(CP(MCSPI1_CLK) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_clk */ \ + MV(CP(MCSPI1_SOMI) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_somi */ \ + MV(CP(MCSPI1_SIMO) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_simo */ \ + MV(CP(MCSPI1_CS0) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_cs0 */ \ + MV(CP(MCSPI1_CS1) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* mcspi1_cs1 */ \ + MV(CP(MCSPI1_CS2) , ( PTU | OFF_EN | OFF_OUT_PTU | M3)) /* gpio_139 */ \ + MV(CP(MCSPI1_CS3) , ( PTU | IEN | M3)) /* gpio_140 */ \ + MV(CP(UART3_CTS_RCTX) , ( PTU | IEN | M0)) /* uart3_tx */ \ + MV(CP(UART3_RTS_SD) , ( M0)) /* uart3_rts_sd */ \ + MV(CP(UART3_RX_IRRX) , ( IEN | M0)) /* uart3_rx */ \ + MV(CP(UART3_TX_IRTX) , ( M0)) /* uart3_tx */ \ + MV(CP(SDMMC5_CLK) , ( PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)) /* sdmmc5_clk */ \ + MV(CP(SDMMC5_CMD) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_cmd */ \ + MV(CP(SDMMC5_DAT0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat0 */ \ + MV(CP(SDMMC5_DAT1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat1 */ \ + MV(CP(SDMMC5_DAT2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat2 */ \ + MV(CP(SDMMC5_DAT3) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat3 */ \ + MV(CP(MCSPI4_CLK) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_clk */ \ + MV(CP(MCSPI4_SIMO) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_simo */ \ + MV(CP(MCSPI4_SOMI) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_somi */ \ + MV(CP(MCSPI4_CS0) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_cs0 */ \ + MV(CP(UART4_RX) , ( IEN | M0)) /* uart4_rx */ \ + MV(CP(UART4_TX) , ( M0)) /* uart4_tx */ \ + MV(CP(USBB2_ULPITLL_CLK) , ( IEN | M3)) /* gpio_157 */ \ + MV(CP(USBB2_ULPITLL_STP) , ( IEN | M5)) /* dispc2_data23 */ \ + MV(CP(USBB2_ULPITLL_DIR) , ( IEN | M5)) /* dispc2_data22 */ \ + MV(CP(USBB2_ULPITLL_NXT) , ( IEN | M5)) /* dispc2_data21 */ \ + MV(CP(USBB2_ULPITLL_DAT0) , ( IEN | M5)) /* dispc2_data20 */ \ + MV(CP(USBB2_ULPITLL_DAT1) , ( IEN | M5)) /* dispc2_data19 */ \ + MV(CP(USBB2_ULPITLL_DAT2) , ( IEN | M5)) /* dispc2_data18 */ \ + MV(CP(USBB2_ULPITLL_DAT3) , ( IEN | M5)) /* dispc2_data15 */ \ + MV(CP(USBB2_ULPITLL_DAT4) , ( IEN | M5)) /* dispc2_data14 */ \ + MV(CP(USBB2_ULPITLL_DAT5) , ( IEN | M5)) /* dispc2_data13 */ \ + MV(CP(USBB2_ULPITLL_DAT6) , ( IEN | M5)) /* dispc2_data12 */ \ + MV(CP(USBB2_ULPITLL_DAT7) , ( IEN | M5)) /* dispc2_data11 */ \ + MV(CP(USBB2_HSIC_DATA) , ( PTD | OFF_EN | OFF_OUT_PTU | M3)) /* gpio_169 */ \ + MV(CP(USBB2_HSIC_STROBE) , ( PTD | OFF_EN | OFF_OUT_PTU | M3)) /* gpio_170 */ \ + MV(CP(UNIPRO_TX0) , ( PTD | IEN | M3)) /* gpio_171 */ \ + MV(CP(UNIPRO_TY0) , ( OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col1 */ \ + MV(CP(UNIPRO_TX1) , ( OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col2 */ \ + MV(CP(UNIPRO_TY1) , ( OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col3 */ \ + MV(CP(UNIPRO_TX2) , ( PTU | IEN | M3)) /* gpio_0 */ \ + MV(CP(UNIPRO_TY2) , ( PTU | IEN | M3)) /* gpio_1 */ \ + MV(CP(UNIPRO_RX0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row0 */ \ + MV(CP(UNIPRO_RY0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row1 */ \ + MV(CP(UNIPRO_RX1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row2 */ \ + MV(CP(UNIPRO_RY1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row3 */ \ + MV(CP(UNIPRO_RX2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row4 */ \ + MV(CP(UNIPRO_RY2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row5 */ \ + MV(CP(USBA0_OTG_CE) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* usba0_otg_ce */ \ + MV(CP(USBA0_OTG_DP) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usba0_otg_dp */ \ + MV(CP(USBA0_OTG_DM) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usba0_otg_dm */ \ + MV(CP(FREF_CLK1_OUT) , ( M0)) /* fref_clk1_out */ \ + MV(CP(FREF_CLK2_OUT) , ( PTD | IEN | M3)) /* gpio_182 */ \ + MV(CP(SYS_NIRQ1) , ( PTU | IEN | M0)) /* sys_nirq1 */ \ + MV(CP(SYS_NIRQ2) , ( PTU | IEN | M0)) /* sys_nirq2 */ \ + MV(CP(SYS_BOOT0) , ( PTU | IEN | M3)) /* gpio_184 */ \ + MV(CP(SYS_BOOT1) , ( M3)) /* gpio_185 */ \ + MV(CP(SYS_BOOT2) , ( PTD | IEN | M3)) /* gpio_186 */ \ + MV(CP(SYS_BOOT3) , ( M3)) /* gpio_187 */ \ + MV(CP(SYS_BOOT4) , ( M3)) /* gpio_188 */ \ + MV(CP(SYS_BOOT5) , ( PTD | IEN | M3)) /* gpio_189 */ \ + MV(CP(DPM_EMU0) , ( IEN | M0)) /* dpm_emu0 */ \ + MV(CP(DPM_EMU1) , ( IEN | M0)) /* dpm_emu1 */ \ + MV(CP(DPM_EMU2) , ( IEN | M0)) /* dpm_emu2 */ \ + MV(CP(DPM_EMU3) , ( IEN | M5)) /* dispc2_data10 */ \ + MV(CP(DPM_EMU4) , ( IEN | M5)) /* dispc2_data9 */ \ + MV(CP(DPM_EMU5) , ( IEN | M5)) /* dispc2_data16 */ \ + MV(CP(DPM_EMU6) , ( IEN | M5)) /* dispc2_data17 */ \ + MV(CP(DPM_EMU7) , ( IEN | M5)) /* dispc2_hsync */ \ + MV(CP(DPM_EMU8) , ( IEN | M5)) /* dispc2_pclk */ \ + MV(CP(DPM_EMU9) , ( IEN | M5)) /* dispc2_vsync */ \ + MV(CP(DPM_EMU10) , ( IEN | M5)) /* dispc2_de */ \ + MV(CP(DPM_EMU11) , ( IEN | M5)) /* dispc2_data8 */ \ + MV(CP(DPM_EMU12) , ( IEN | M5)) /* dispc2_data7 */ \ + MV(CP(DPM_EMU13) , ( IEN | M5)) /* dispc2_data6 */ \ + MV(CP(DPM_EMU14) , ( IEN | M5)) /* dispc2_data5 */ \ + MV(CP(DPM_EMU15) , ( IEN | M5)) /* dispc2_data4 */ \ + MV(CP(DPM_EMU16) , ( M3)) /* gpio_27 */ \ + MV(CP(DPM_EMU17) , ( IEN | M5)) /* dispc2_data2 */ \ + MV(CP(DPM_EMU18) , ( IEN | M5)) /* dispc2_data1 */ \ + MV(CP(DPM_EMU19) , ( IEN | M5)) /* dispc2_data0 */ \ + MV1(WK(PAD0_SIM_IO) , ( IEN | M0)) /* sim_io */ \ + MV1(WK(PAD1_SIM_CLK) , ( M0)) /* sim_clk */ \ + MV1(WK(PAD0_SIM_RESET) , ( M0)) /* sim_reset */ \ + MV1(WK(PAD1_SIM_CD) , ( PTU | IEN | M0)) /* sim_cd */ \ + MV1(WK(PAD0_SIM_PWRCTRL) , ( M0)) /* sim_pwrctrl */ \ + MV1(WK(PAD1_SR_SCL) , ( PTU | IEN | M0)) /* sr_scl */ \ + MV1(WK(PAD0_SR_SDA) , ( PTU | IEN | M0)) /* sr_sda */ \ + MV1(WK(PAD1_FREF_XTAL_IN) , ( M0)) /* # */ \ + MV1(WK(PAD0_FREF_SLICER_IN) , ( M0)) /* fref_slicer_in */ \ + MV1(WK(PAD1_FREF_CLK_IOREQ) , ( M0)) /* fref_clk_ioreq */ \ + MV1(WK(PAD0_FREF_CLK0_OUT) , ( M2)) /* sys_drm_msecure */ \ + MV1(WK(PAD1_FREF_CLK3_REQ) , ( PTU | IEN | M0)) /* # */ \ + MV1(WK(PAD0_FREF_CLK3_OUT) , ( M0)) /* fref_clk3_out */ \ + MV1(WK(PAD1_FREF_CLK4_REQ) , ( PTU | IEN | M0)) /* # */ \ + MV1(WK(PAD0_FREF_CLK4_OUT) , ( M0)) /* # */ \ + MV1(WK(PAD1_SYS_32K) , ( IEN | M0)) /* sys_32k */ \ + MV1(WK(PAD0_SYS_NRESPWRON) , ( M0)) /* sys_nrespwron */ \ + MV1(WK(PAD1_SYS_NRESWARM) , ( M0)) /* sys_nreswarm */ \ + MV1(WK(PAD0_SYS_PWR_REQ) , ( PTU | M0)) /* sys_pwr_req */ \ + MV1(WK(PAD1_SYS_PWRON_RESET) , ( M3)) /* gpio_wk29 */ \ + MV1(WK(PAD0_SYS_BOOT6) , ( IEN | M3)) /* gpio_wk9 */ \ + MV1(WK(PAD1_SYS_BOOT7) , ( IEN | M3)) /* gpio_wk10 */ \ + MV1(WK(PAD1_FREF_CLK3_REQ), (M3)) /* gpio_wk30 */ \ + MV1(WK(PAD1_FREF_CLK4_REQ), (M3)) /* gpio_wk7 */ \ + MV1(WK(PAD0_FREF_CLK4_OUT), (M3)) /* gpio_wk8 */ + +#define MUX_DEFAULT_OMAP4_ALL() \ + MV(CP(GPMC_AD0), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat0 */ \ + MV(CP(GPMC_AD1), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat1 */ \ + MV(CP(GPMC_AD2), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat2 */ \ + MV(CP(GPMC_AD3), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat3 */ \ + MV(CP(GPMC_AD4), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat4 */ \ + MV(CP(GPMC_AD5), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat5 */ \ + MV(CP(GPMC_AD6), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat6 */ \ + MV(CP(GPMC_AD7), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat7 */ \ + MV(CP(GPMC_AD8), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpio_32 */ \ + MV(CP(GPMC_AD9), (M3_SAFE)) /* gpio_33 */ \ + MV(CP(GPMC_AD10), (M3_SAFE)) /* gpio_34 */ \ + MV(CP(GPMC_AD11), (M3_SAFE)) /* gpio_35 */ \ + MV(CP(GPMC_AD12), (M3_SAFE)) /* gpio_36 */ \ + MV(CP(GPMC_AD13), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_37 */ \ + MV(CP(GPMC_AD14), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_38 */ \ + MV(CP(GPMC_AD15), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_39 */ \ + MV(CP(GPMC_A16), (M3_SAFE)) /* gpio_40 */ \ + MV(CP(GPMC_A17), (M3_SAFE)) /* gpio_41 */ \ + MV(CP(GPMC_A18), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row6 */ \ + MV(CP(GPMC_A19), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row7 */ \ + MV(CP(GPMC_A20), (M3_SAFE)) /* gpio_44 */ \ + MV(CP(GPMC_A21), (M3_SAFE)) /* gpio_45 */ \ + MV(CP(GPMC_A22), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col6 */ \ + MV(CP(GPMC_A23), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col7 */ \ + MV(CP(GPMC_A24), (M3_SAFE)) /* gpio_48 */ \ + MV(CP(GPMC_A25), (M3_SAFE)) /* gpio_49 */ \ + MV(CP(GPMC_NCS0), (M0)) /* gpmc_ncs0 */ \ + MV(CP(GPMC_NCS1), (M3_SAFE)) /* gpio_51 */ \ + MV(CP(GPMC_NCS2), (M3_SAFE)) /* gpio_52 */ \ + MV(CP(GPMC_NCS3), (M3_SAFE)) /* gpio_53 */ \ + MV(CP(GPMC_NWP), (M0_SAFE)) /* gpmc_nwp */ \ + MV(CP(GPMC_CLK), (M3_SAFE)) /* gpio_55 */ \ + MV(CP(GPMC_NADV_ALE), (M0)) /* gpmc_nadv_ale */ \ + MV(CP(GPMC_NOE), (PTU | OFF_EN | OFF_OUT_PTD | M1)) /* sdmmc2_clk */ \ + MV(CP(GPMC_NWE), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_cmd */ \ + MV(CP(GPMC_NBE0_CLE), (M0)) /* gpmc_nbe0_cle*/ \ + MV(CP(GPMC_NBE1), (M3_SAFE)) /* gpio_60 */ \ + MV(CP(GPMC_WAIT0), (M0)) /* gpmc_wait */ \ + MV(CP(GPMC_WAIT1), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_39 */ \ + MV(CP(C2C_DATA11), (M3_SAFE)) /* gpio_100 */ \ + MV(CP(C2C_DATA12), (M1_SAFE)) /* dsi1_te0 */ \ + MV(CP(C2C_DATA13), (M3_SAFE)) /* gpio_102 */ \ + MV(CP(C2C_DATA14), (M1_SAFE)) /* dsi2_te0 */ \ + MV(CP(C2C_DATA15), (M3_SAFE)) /* gpio_104 */ \ + MV(CP(HDMI_HPD), (M0_SAFE)) /* hdmi_hpd */ \ + MV(CP(HDMI_CEC), (M0_SAFE)) /* hdmi_cec */ \ + MV(CP(HDMI_DDC_SCL), (M0_SAFE)) /* hdmi_ddc_scl */ \ + MV(CP(HDMI_DDC_SDA), (M0_SAFE)) /* hdmi_ddc_sda */ \ + MV(CP(CSI21_DX0), (M0_SAFE)) /* csi21_dx0 */ \ + MV(CP(CSI21_DY0), (M0_SAFE)) /* csi21_dy0 */ \ + MV(CP(CSI21_DX1), (M0_SAFE)) /* csi21_dx1 */ \ + MV(CP(CSI21_DY1), (M0_SAFE)) /* csi21_dy1 */ \ + MV(CP(CSI21_DX2), (M0_SAFE)) /* csi21_dx2 */ \ + MV(CP(CSI21_DY2), (M0_SAFE)) /* csi21_dy2 */ \ + MV(CP(CSI21_DX3), (M0_SAFE)) /* csi21_dx3 */ \ + MV(CP(CSI21_DY3), (M0_SAFE)) /* csi21_dy3 */ \ + MV(CP(CSI21_DX4), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpi_75 */ \ + MV(CP(CSI21_DY4), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpi_76 */ \ + MV(CP(CSI22_DX0), (M0_SAFE)) /* csi22_dx0 */ \ + MV(CP(CSI22_DY0), (M0_SAFE)) /* csi22_dy0 */ \ + MV(CP(CSI22_DX1), (M0_SAFE)) /* csi22_dx1 */ \ + MV(CP(CSI22_DY1), (M0_SAFE)) /* csi22_dy1 */ \ + MV(CP(CAM_SHUTTER), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* cam_shutter */ \ + MV(CP(CAM_STROBE), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* cam_strobe */ \ + MV(CP(CAM_GLOBALRESET), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_83 */ \ + MV(CP(USBB1_ULPITLL_CLK), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_clk */ \ + MV(CP(USBB1_ULPITLL_STP), (PTU | OFF_EN | OFF_OUT_PTD | M4)) /* usbb1_ulpiphy_stp */ \ + MV(CP(USBB1_ULPITLL_DIR), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dir */ \ + MV(CP(USBB1_ULPITLL_NXT), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_nxt */ \ + MV(CP(USBB1_ULPITLL_DAT0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat0 */ \ + MV(CP(USBB1_ULPITLL_DAT1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat1 */ \ + MV(CP(USBB1_ULPITLL_DAT2), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat2 */ \ + MV(CP(USBB1_ULPITLL_DAT3), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat3 */ \ + MV(CP(USBB1_ULPITLL_DAT4), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat4 */ \ + MV(CP(USBB1_ULPITLL_DAT5), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat5 */ \ + MV(CP(USBB1_ULPITLL_DAT6), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat6 */ \ + MV(CP(USBB1_ULPITLL_DAT7), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat7 */ \ + MV(CP(USBB1_HSIC_DATA), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usbb1_hsic_data */ \ + MV(CP(USBB1_HSIC_STROBE), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usbb1_hsic_strobe */ \ + MV(CP(USBC1_ICUSB_DP), (M0_SAFE)) /* usbc1_icusb_dp */ \ + MV(CP(USBC1_ICUSB_DM), (M0_SAFE)) /* usbc1_icusb_dm */ \ + MV(CP(SDMMC1_CLK), (PTU | OFF_EN | OFF_OUT_PTD | M0)) /* sdmmc1_clk */ \ + MV(CP(SDMMC1_CMD), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_cmd */ \ + MV(CP(SDMMC1_DAT0), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat0 */ \ + MV(CP(SDMMC1_DAT1), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat1 */ \ + MV(CP(SDMMC1_DAT2), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat2 */ \ + MV(CP(SDMMC1_DAT3), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat3 */ \ + MV(CP(SDMMC1_DAT4), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat4 */ \ + MV(CP(SDMMC1_DAT5), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat5 */ \ + MV(CP(SDMMC1_DAT6), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat6 */ \ + MV(CP(SDMMC1_DAT7), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat7 */ \ + MV(CP(ABE_MCBSP2_CLKX), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp2_clkx */ \ + MV(CP(ABE_MCBSP2_DR), (IEN | OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp2_dr */ \ + MV(CP(ABE_MCBSP2_DX), (OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp2_dx */ \ + MV(CP(ABE_MCBSP2_FSX), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp2_fsx */ \ + MV(CP(ABE_MCBSP1_CLKX), (M1_SAFE)) /* abe_slimbus1_clock */ \ + MV(CP(ABE_MCBSP1_DR), (M1_SAFE)) /* abe_slimbus1_data */ \ + MV(CP(ABE_MCBSP1_DX), (OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp1_dx */ \ + MV(CP(ABE_MCBSP1_FSX), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp1_fsx */ \ + MV(CP(ABE_PDM_UL_DATA), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_pdm_ul_data */ \ + MV(CP(ABE_PDM_DL_DATA), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_pdm_dl_data */ \ + MV(CP(ABE_PDM_FRAME), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_pdm_frame */ \ + MV(CP(ABE_PDM_LB_CLK), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_pdm_lb_clk */ \ + MV(CP(ABE_CLKS), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_clks */ \ + MV(CP(ABE_DMIC_CLK1), (M0_SAFE)) /* abe_dmic_clk1 */ \ + MV(CP(ABE_DMIC_DIN1), (M0_SAFE)) /* abe_dmic_din1 */ \ + MV(CP(ABE_DMIC_DIN2), (M0_SAFE)) /* abe_dmic_din2 */ \ + MV(CP(ABE_DMIC_DIN3), (M0_SAFE)) /* abe_dmic_din3 */ \ + MV(CP(UART2_CTS), (PTU | IEN | M0)) /* uart2_cts */ \ + MV(CP(UART2_RTS), (M0)) /* uart2_rts */ \ + MV(CP(UART2_RX), (PTU | IEN | M0)) /* uart2_rx */ \ + MV(CP(UART2_TX), (M0)) /* uart2_tx */ \ + MV(CP(HDQ_SIO), (M3_SAFE)) /* gpio_127 */ \ + MV(CP(I2C1_SCL), (PTU | IEN | M0)) /* i2c1_scl */ \ + MV(CP(I2C1_SDA), (PTU | IEN | M0)) /* i2c1_sda */ \ + MV(CP(I2C2_SCL), (PTU | IEN | M0)) /* i2c2_scl */ \ + MV(CP(I2C2_SDA), (PTU | IEN | M0)) /* i2c2_sda */ \ + MV(CP(I2C3_SCL), (PTU | IEN | M0)) /* i2c3_scl */ \ + MV(CP(I2C3_SDA), (PTU | IEN | M0)) /* i2c3_sda */ \ + MV(CP(I2C4_SCL), (PTU | IEN | M0)) /* i2c4_scl */ \ + MV(CP(I2C4_SDA), (PTU | IEN | M0)) /* i2c4_sda */ \ + MV(CP(MCSPI1_CLK), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_clk */ \ + MV(CP(MCSPI1_SOMI), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_somi */ \ + MV(CP(MCSPI1_SIMO), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_simo */ \ + MV(CP(MCSPI1_CS0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_cs0 */ \ + MV(CP(MCSPI1_CS1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* mcspi1_cs1 */ \ + MV(CP(MCSPI1_CS2), (OFF_EN | OFF_OUT_PTU | M3)) /* gpio_139 */ \ + MV(CP(MCSPI1_CS3), (M3_SAFE)) /* gpio_140 */ \ + MV(CP(UART3_CTS_RCTX), (PTU | IEN | M0)) /* uart3_tx */ \ + MV(CP(UART3_RTS_SD), (M0)) /* uart3_rts_sd */ \ + MV(CP(UART3_RX_IRRX), (IEN | M0)) /* uart3_rx */ \ + MV(CP(UART3_TX_IRTX), (M0)) /* uart3_tx */ \ + MV(CP(SDMMC5_CLK), (PTU | OFF_EN | OFF_OUT_PTD | M0)) /* sdmmc5_clk */ \ + MV(CP(SDMMC5_CMD), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_cmd */ \ + MV(CP(SDMMC5_DAT0), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat0 */ \ + MV(CP(SDMMC5_DAT1), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat1 */ \ + MV(CP(SDMMC5_DAT2), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat2 */ \ + MV(CP(SDMMC5_DAT3), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat3 */ \ + MV(CP(MCSPI4_CLK), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_clk */ \ + MV(CP(MCSPI4_SIMO), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_simo */ \ + MV(CP(MCSPI4_SOMI), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_somi */ \ + MV(CP(MCSPI4_CS0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_cs0 */ \ + MV(CP(UART4_RX), (IEN | M0)) /* uart4_rx */ \ + MV(CP(UART4_TX), (M0)) /* uart4_tx */ \ + MV(CP(USBB2_ULPITLL_CLK), (M3)) /* gpio_157 */ \ + MV(CP(USBB2_ULPITLL_STP), (M5)) /* dispc2_data23 */ \ + MV(CP(USBB2_ULPITLL_DIR), (M5)) /* dispc2_data22 */ \ + MV(CP(USBB2_ULPITLL_NXT), (M5)) /* dispc2_data21 */ \ + MV(CP(USBB2_ULPITLL_DAT0), (M5)) /* dispc2_data20 */ \ + MV(CP(USBB2_ULPITLL_DAT1), (M5)) /* dispc2_data19 */ \ + MV(CP(USBB2_ULPITLL_DAT2), (M5)) /* dispc2_data18 */ \ + MV(CP(USBB2_ULPITLL_DAT3), (M5)) /* dispc2_data15 */ \ + MV(CP(USBB2_ULPITLL_DAT4), (M5)) /* dispc2_data14 */ \ + MV(CP(USBB2_ULPITLL_DAT5), (M5)) /* dispc2_data13 */ \ + MV(CP(USBB2_ULPITLL_DAT6), (M5)) /* dispc2_data12 */ \ + MV(CP(USBB2_ULPITLL_DAT7), (M5)) /* dispc2_data11 */ \ + MV(CP(USBB2_HSIC_DATA), (OFF_EN | OFF_OUT_PTU | M3)) /* gpio_169 */ \ + MV(CP(USBB2_HSIC_STROBE), (OFF_EN | OFF_OUT_PTU | M3)) /* gpio_170 */ \ + MV(CP(UNIPRO_TX0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col0 */ \ + MV(CP(UNIPRO_TY0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col1 */ \ + MV(CP(UNIPRO_TX1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col2 */ \ + MV(CP(UNIPRO_TY1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col3 */ \ + MV(CP(UNIPRO_TX2), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpio_0 */ \ + MV(CP(UNIPRO_TY2), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpio_1 */ \ + MV(CP(UNIPRO_RX0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row0 */ \ + MV(CP(UNIPRO_RY0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row1 */ \ + MV(CP(UNIPRO_RX1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row2 */ \ + MV(CP(UNIPRO_RY1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row3 */ \ + MV(CP(UNIPRO_RX2), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row4 */ \ + MV(CP(UNIPRO_RY2), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row5 */ \ + MV(CP(USBA0_OTG_CE), (PTU | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* usba0_otg_ce */ \ + MV(CP(USBA0_OTG_DP), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usba0_otg_dp */ \ + MV(CP(USBA0_OTG_DM), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usba0_otg_dm */ \ + MV(CP(FREF_CLK1_OUT), (M0_SAFE)) /* fref_clk1_out */ \ + MV(CP(FREF_CLK2_OUT), (M0_SAFE)) /* fref_clk2_out */ \ + MV(CP(SYS_NIRQ1), (PTU | IEN | M0)) /* sys_nirq1 */ \ + MV(CP(SYS_NIRQ2), (PTU | IEN | M0)) /* sys_nirq2 */ \ + MV(CP(SYS_BOOT0), (M3_SAFE)) /* gpio_184 */ \ + MV(CP(SYS_BOOT1), (M3_SAFE)) /* gpio_185 */ \ + MV(CP(SYS_BOOT2), (M3_SAFE)) /* gpio_186 */ \ + MV(CP(SYS_BOOT3), (M3_SAFE)) /* gpio_187 */ \ + MV(CP(SYS_BOOT4), (M3_SAFE)) /* gpio_188 */ \ + MV(CP(SYS_BOOT5), (M3_SAFE)) /* gpio_189 */ \ + MV(CP(DPM_EMU0), (M0_SAFE)) /* dpm_emu0 */ \ + MV(CP(DPM_EMU1), (M0_SAFE)) /* dpm_emu1 */ \ + MV(CP(DPM_EMU2), (M0_SAFE)) /* dpm_emu2 */ \ + MV(CP(DPM_EMU3), (M5)) /* dispc2_data10 */ \ + MV(CP(DPM_EMU4), (M5)) /* dispc2_data9 */ \ + MV(CP(DPM_EMU5), (M5)) /* dispc2_data16 */ \ + MV(CP(DPM_EMU6), (M5)) /* dispc2_data17 */ \ + MV(CP(DPM_EMU7), (M5)) /* dispc2_hsync */ \ + MV(CP(DPM_EMU8), (M5)) /* dispc2_pclk */ \ + MV(CP(DPM_EMU9), (M5)) /* dispc2_vsync */ \ + MV(CP(DPM_EMU10), (M5)) /* dispc2_de */ \ + MV(CP(DPM_EMU11), (M5)) /* dispc2_data8 */ \ + MV(CP(DPM_EMU12), (M5)) /* dispc2_data7 */ \ + MV(CP(DPM_EMU13), (M5)) /* dispc2_data6 */ \ + MV(CP(DPM_EMU14), (M5)) /* dispc2_data5 */ \ + MV(CP(DPM_EMU15), (M5)) /* dispc2_data4 */ \ + MV(CP(DPM_EMU16), (M5)) /* dispc2_data3/dmtimer8_pwm_evt */ \ + MV(CP(DPM_EMU17), (M5)) /* dispc2_data2 */ \ + MV(CP(DPM_EMU18), (M5)) /* dispc2_data1 */ \ + MV(CP(DPM_EMU19), (M5)) /* dispc2_data0 */ \ + MV1(WK(PAD0_SIM_IO), (M0_SAFE)) /* sim_io */ \ + MV1(WK(PAD1_SIM_CLK), (M0_SAFE)) /* sim_clk */ \ + MV1(WK(PAD0_SIM_RESET), (M0_SAFE)) /* sim_reset */ \ + MV1(WK(PAD1_SIM_CD), (M0_SAFE)) /* sim_cd */ \ + MV1(WK(PAD0_SIM_PWRCTRL), (M0_SAFE)) /* sim_pwrctrl */ \ + MV1(WK(PAD1_SR_SCL), (PTU | IEN | M0)) /* sr_scl */ \ + MV1(WK(PAD0_SR_SDA), (PTU | IEN | M0)) /* sr_sda */ \ + MV1(WK(PAD1_FREF_XTAL_IN), (M0_SAFE)) /* # */ \ + MV1(WK(PAD0_FREF_SLICER_IN), (M0_SAFE)) /* fref_slicer_in */ \ + MV1(WK(PAD1_FREF_CLK_IOREQ), (M0_SAFE)) /* fref_clk_ioreq */ \ + MV1(WK(PAD0_FREF_CLK0_OUT), (M0)) /* sys_drm_msecure */ \ + MV1(WK(PAD1_FREF_CLK3_REQ), (M0)) /* # */ \ + MV1(WK(PAD0_FREF_CLK3_OUT), (M0_SAFE)) /* fref_clk3_out */ \ + MV1(WK(PAD1_FREF_CLK4_REQ), (M0_SAFE)) /* # */ \ + MV1(WK(PAD0_FREF_CLK4_OUT), (M0_SAFE)) /* # */ \ + MV1(WK(PAD1_SYS_32K), (IEN | M0_SAFE)) /* sys_32k */ \ + MV1(WK(PAD0_SYS_NRESPWRON), (IEN | M0_SAFE)) /* sys_nrespwron */ \ + MV1(WK(PAD1_SYS_NRESWARM), (IEN | M0_SAFE)) /* sys_nreswarm */ \ + MV1(WK(PAD0_SYS_PWR_REQ), (M0_SAFE)) /* sys_pwr_req */ \ + MV1(WK(PAD1_SYS_PWRON_RESET), (M3_SAFE)) /* gpio_wk29 */ \ + MV1(WK(PAD0_SYS_BOOT6), (M3_SAFE)) /* gpio_wk9 */ \ + MV1(WK(PAD1_SYS_BOOT7), (M3_SAFE)) /* gpio_wk10 */ \ + MV1(WK(PAD1_JTAG_TCK), (IEN | M0)) /* jtag_tck */ \ + MV1(WK(PAD0_JTAG_RTCK), (M0)) /* jtag_rtck */ \ + MV1(WK(PAD1_JTAG_TMS_TMSC), (IEN | M0)) /* jtag_tms_tmsc */ \ + MV1(WK(PAD0_JTAG_TDI), (IEN | M0)) /* jtag_tdi */ \ + MV1(WK(PAD1_JTAG_TDO), (M0)) /* jtag_tdo */ + +/********************************************************** + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers + * specific to the hardware. Many pins need + * to be moved from protect to primary mode. + *********************************************************/ +void set_muxconf_regs(void) +{ + MUX_DEFAULT_OMAP4(); + return; +} + +/****************************************************************************** + * Routine: update_mux() + * Description:Update balls which are different between boards. All should be + * updated to match functionality. However, I'm only updating ones + * which I'll be using for now. When power comes into play they + * all need updating. + *****************************************************************************/ +void update_mux(u32 btype, u32 mtype) +{ + /* REVISIT */ + return; + +} + +/* optionally do something like blinking LED */ +void board_hang (void) +{ while (0) {};} + +int nand_init(void) +{ + return 0; +} +void reset_phy(unsigned int base) +{ + *(volatile int*)(base + IODFT_TLGC) |= (1 << 10); +} diff --git a/board/omap4430panda/platform.S b/board/omap4430panda/platform.S new file mode 100644 index 0000000..2eff964 --- /dev/null +++ b/board/omap4430panda/platform.S @@ -0,0 +1,51 @@ +/* + * Board specific setup info + * + * (C) Copyright 2004-2006 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/arch/cpu.h> +#include <asm/arch/mem.h> +#include <asm/arch/clocks.h> + +_TEXT_BASE: + .word TEXT_BASE /* sdram load addr from config.mk */ + +.globl lowlevel_init +lowlevel_init: + ldr sp, SRAM_STACK + str ip, [sp] /* stash old link register */ + mov ip, lr /* save link reg across call */ + bl s_init /* go setup pll,mux,memory */ + ldr ip, [sp] /* restore save ip */ + mov lr, ip /* restore link reg */ + + /* back to arch calling code */ + mov pc, lr + + /* the literal pools origin */ + .ltorg + +SRAM_STACK: + .word LOW_LEVEL_SRAM_STACK diff --git a/board/omap4430panda/syslib.c b/board/omap4430panda/syslib.c new file mode 100644 index 0000000..2b16cc4 --- /dev/null +++ b/board/omap4430panda/syslib.c @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2006 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/cpu.h> +#include <asm/io.h> +#include <asm/arch/bits.h> +#include <asm/arch/mem.h> +#include <asm/arch/clocks.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/sys_info.h> + +/************************************************************ + * sdelay() - simple spin loop. Will be constant time as + * its generally used in bypass conditions only. This + * is necessary until timers are accessible. + * + * not inline to increase chances its in cache when called + *************************************************************/ +void sdelay(unsigned long loops) +{ + __asm__ volatile ("1:\n" "subs %0, %1, #1\n" + "bne 1b":"=r" (loops):"0"(loops)); +} + +/***************************************************************** + * sr32 - clear & set a value in a bit range for a 32 bit address + *****************************************************************/ +void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value) +{ + u32 tmp, msk = 0; + msk = 1 << num_bits; + --msk; + tmp = __raw_readl(addr) & ~(msk << start_bit); + tmp |= value << start_bit; + __raw_writel(tmp, addr); +} + +/********************************************************************* + * wait_on_value() - common routine to allow waiting for changes in + * volatile regs. + *********************************************************************/ +u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) +{ + u32 i = 0, val; + do { + ++i; + val = __raw_readl(read_addr) & read_bit_mask; + if (val == match_value) + return (1); + if (i == bound) + return (0); + } while (1); +} + |