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| author | Evan Cheng <evan.cheng@apple.com> | 2009-10-22 06:48:32 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2009-10-22 06:48:32 +0000 |
| commit | 2147b5787db9e84e22c5d008db703ddce3ae9d86 (patch) | |
| tree | 93b4aa09851a4db76efa8ed5da96d9ea6cacdc8f | |
| parent | de6ba0a0863d45638958b1c0e47aab50c9fbaaa0 (diff) | |
| download | external_llvm-2147b5787db9e84e22c5d008db703ddce3ae9d86.zip external_llvm-2147b5787db9e84e22c5d008db703ddce3ae9d86.tar.gz external_llvm-2147b5787db9e84e22c5d008db703ddce3ae9d86.tar.bz2 | |
Move if-conversion before post-regalloc scheduling so the predicated instruction get scheduled properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84843 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMTargetMachine.cpp | 8 | ||||
| -rw-r--r-- | test/CodeGen/ARM/ifcvt5.ll | 3 |
2 files changed, 5 insertions, 6 deletions
diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp index c1da6ce..bd2e734 100644 --- a/lib/Target/ARM/ARMTargetMachine.cpp +++ b/lib/Target/ARM/ARMTargetMachine.cpp @@ -103,18 +103,16 @@ bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM, bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { // FIXME: temporarily disabling load / store optimization pass for Thumb1. - if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) + if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) { PM.add(createARMLoadStoreOptimizationPass()); + PM.add(createIfConverterPass()); + } return true; } bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { - // FIXME: temporarily disabling load / store optimization pass for Thumb1. - if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) - PM.add(createIfConverterPass()); - if (Subtarget.isThumb2()) { PM.add(createThumb2ITBlockPass()); PM.add(createThumb2SizeReductionPass()); diff --git a/test/CodeGen/ARM/ifcvt5.ll b/test/CodeGen/ARM/ifcvt5.ll index e9145ac..92bbe75 100644 --- a/test/CodeGen/ARM/ifcvt5.ll +++ b/test/CodeGen/ARM/ifcvt5.ll @@ -11,7 +11,8 @@ entry: define void @t1(i32 %a, i32 %b) { ; CHECK: t1: -; CHECK: ldmltfd sp!, {r7, pc} +; CHECK: movge +; CHECK: blge _foo entry: %tmp1 = icmp sgt i32 %a, 10 ; <i1> [#uses=1] br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock |