diff options
| -rw-r--r-- | lib/Target/ARM/ARMTargetMachine.cpp | 8 | ||||
| -rw-r--r-- | test/CodeGen/ARM/ifcvt5.ll | 3 |
2 files changed, 5 insertions, 6 deletions
diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp index c1da6ce..bd2e734 100644 --- a/lib/Target/ARM/ARMTargetMachine.cpp +++ b/lib/Target/ARM/ARMTargetMachine.cpp @@ -103,18 +103,16 @@ bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM, bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { // FIXME: temporarily disabling load / store optimization pass for Thumb1. - if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) + if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) { PM.add(createARMLoadStoreOptimizationPass()); + PM.add(createIfConverterPass()); + } return true; } bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { - // FIXME: temporarily disabling load / store optimization pass for Thumb1. - if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) - PM.add(createIfConverterPass()); - if (Subtarget.isThumb2()) { PM.add(createThumb2ITBlockPass()); PM.add(createThumb2SizeReductionPass()); diff --git a/test/CodeGen/ARM/ifcvt5.ll b/test/CodeGen/ARM/ifcvt5.ll index e9145ac..92bbe75 100644 --- a/test/CodeGen/ARM/ifcvt5.ll +++ b/test/CodeGen/ARM/ifcvt5.ll @@ -11,7 +11,8 @@ entry: define void @t1(i32 %a, i32 %b) { ; CHECK: t1: -; CHECK: ldmltfd sp!, {r7, pc} +; CHECK: movge +; CHECK: blge _foo entry: %tmp1 = icmp sgt i32 %a, 10 ; <i1> [#uses=1] br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock |