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authorOwen Anderson <resistor@mac.com>2010-11-17 22:16:31 +0000
committerOwen Anderson <resistor@mac.com>2010-11-17 22:16:31 +0000
commit2f7aed39a3082a3e0bb35475e8ed0cb782fef4b5 (patch)
tree129a93b1faafc9b50f1446bdf8573fac58936316
parent0129be281eea2c22a925873f2e1cd5cc978ae87c (diff)
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Second attempt at correct encodings for Thumb2 bitfield instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119575 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/ARM/ARMInstrThumb2.td57
-rw-r--r--test/MC/ARM/thumb2.s11
2 files changed, 55 insertions, 13 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index ace1333..87e360d 100644
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -1989,27 +1989,54 @@ defm t2BIC : T2I_bin_w_irs<0b0001, "bic",
IIC_iBITi, IIC_iBITr, IIC_iBITsi,
BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
-let Constraints = "$src = $dst" in
-def t2BFC : T2I<(outs rGPR:$dst), (ins rGPR:$src, bf_inv_mask_imm:$imm),
- IIC_iUNAsi, "bfc", "\t$dst, $imm",
- [(set rGPR:$dst, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
+class T2BitFI<dag oops, dag iops, InstrItinClass itin,
+ string opc, string asm, list<dag> pattern>
+ : T2I<oops, iops, itin, opc, asm, pattern> {
+ bits<4> Rd;
+ bits<5> msb;
+ bits<5> lsb;
+
+ let Inst{11-8} = Rd{3-0};
+ let Inst{4-0} = msb{4-0};
+ let Inst{14-12} = lsb{4-2};
+ let Inst{7-6} = lsb{1-0};
+}
+
+class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
+ string opc, string asm, list<dag> pattern>
+ : T2BitFI<oops, iops, itin, opc, asm, pattern> {
+ bits<4> Rn;
+
+ let Inst{19-16} = Rn{3-0};
+}
+
+let Constraints = "$src = $Rd" in
+def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
+ IIC_iUNAsi, "bfc", "\t$Rd, $imm",
+ [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
let Inst{31-27} = 0b11110;
let Inst{25} = 1;
let Inst{24-20} = 0b10110;
let Inst{19-16} = 0b1111; // Rn
let Inst{15} = 0;
+
+ bits<10> imm;
+ let msb{4-0} = imm{9-5};
+ let lsb{4-0} = imm{4-0};
}
-def t2SBFX: T2I<(outs rGPR:$dst), (ins rGPR:$src, imm0_31:$lsb, imm0_31:$width),
- IIC_iUNAsi, "sbfx", "\t$dst, $src, $lsb, $width", []> {
+def t2SBFX: T2TwoRegBitFI<
+ (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm0_31_m1:$msb),
+ IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
let Inst{31-27} = 0b11110;
let Inst{25} = 1;
let Inst{24-20} = 0b10100;
let Inst{15} = 0;
}
-def t2UBFX: T2I<(outs rGPR:$dst), (ins rGPR:$src, imm0_31:$lsb, imm0_31:$width),
- IIC_iUNAsi, "ubfx", "\t$dst, $src, $lsb, $width", []> {
+def t2UBFX: T2TwoRegBitFI<
+ (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm0_31_m1:$msb),
+ IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
let Inst{31-27} = 0b11110;
let Inst{25} = 1;
let Inst{24-20} = 0b11100;
@@ -2017,16 +2044,20 @@ def t2UBFX: T2I<(outs rGPR:$dst), (ins rGPR:$src, imm0_31:$lsb, imm0_31:$width),
}
// A8.6.18 BFI - Bitfield insert (Encoding T1)
-let Constraints = "$src = $dst" in
-def t2BFI : T2I<(outs rGPR:$dst),
- (ins rGPR:$src, rGPR:$val, bf_inv_mask_imm:$imm),
- IIC_iBITi, "bfi", "\t$dst, $val, $imm",
- [(set rGPR:$dst, (ARMbfi rGPR:$src, rGPR:$val,
+let Constraints = "$src = $Rd" in
+def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
+ (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
+ IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
+ [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
bf_inv_mask_imm:$imm))]> {
let Inst{31-27} = 0b11110;
let Inst{25} = 1;
let Inst{24-20} = 0b10110;
let Inst{15} = 0;
+
+ bits<10> imm;
+ let msb{4-0} = imm{9-5};
+ let lsb{4-0} = imm{4-0};
}
defm t2ORN : T2I_bin_irs<0b0011, "orn",
diff --git a/test/MC/ARM/thumb2.s b/test/MC/ARM/thumb2.s
index eb5336f..8276349 100644
--- a/test/MC/ARM/thumb2.s
+++ b/test/MC/ARM/thumb2.s
@@ -52,3 +52,14 @@
@ CHECK: rrx r0, r0 @ encoding: [0x30,0x00,0x4f,0xea]
rrx r0, r0
+@ CHECK: bfc r0, #4, #20 @ encoding: [0x17,0x10,0x6f,0xf3]
+ bfc r0, #4, #20
+@ CHECK: bfc r0, #0, #23 @ encoding: [0x16,0x00,0x6f,0xf3]
+ bfc r0, #0, #23
+@ CHECK: bfc r0, #12, #20 @ encoding: [0x1f,0x30,0x6f,0xf3]
+ bfc r0, #12, #20
+
+@ CHECK: sbfx r0, r0, #7, #11 @ encoding: [0xca,0x10,0x40,0xf3]
+ sbfx r0, r0, #7, #11
+@ CHECK: ubfx r0, r0, #7, #11 @ encoding: [0xca,0x10,0xc0,0xf3]
+ ubfx r0, r0, #7, #11