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authorJohnny Chen <johnny.chen@apple.com>2011-03-31 19:28:35 +0000
committerJohnny Chen <johnny.chen@apple.com>2011-03-31 19:28:35 +0000
commita52d7da1d8c424276f79b80c89ed045166083730 (patch)
tree0343ac3d49e81cd3835f5fb5c6cbb79db1b7f399
parenta6f74992441c998886bbf26696ea7ec9746df537 (diff)
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Fix single word and unsigned byte data transfer instruction encodings so that
Inst{4} = 0. rdar://problem/9213022 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128662 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/ARM/ARMInstrInfo.td2
-rw-r--r--test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt4
2 files changed, 6 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 7706822..18127f3 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -991,6 +991,7 @@ multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
[(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
bits<4> Rt;
bits<17> shift;
+ let shift{4} = 0; // Inst{4} = 0
let Inst{23} = shift{12}; // U (add = ('U' == 1))
let Inst{19-16} = shift{16-13}; // Rn
let Inst{15-12} = Rt;
@@ -1020,6 +1021,7 @@ multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
[(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
bits<4> Rt;
bits<17> shift;
+ let shift{4} = 0; // Inst{4} = 0
let Inst{23} = shift{12}; // U (add = ('U' == 1))
let Inst{19-16} = shift{16-13}; // Rn
let Inst{15-12} = Rt;
diff --git a/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt b/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt
new file mode 100644
index 0000000..23a0b85
--- /dev/null
+++ b/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt
@@ -0,0 +1,4 @@
+# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
+
+# LDR (register) has encoding Inst{4} = 0.
+0xba 0xae 0x9f 0x57