diff options
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 2 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt | 4 |
2 files changed, 6 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 7706822..18127f3 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -991,6 +991,7 @@ multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii, [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> { bits<4> Rt; bits<17> shift; + let shift{4} = 0; // Inst{4} = 0 let Inst{23} = shift{12}; // U (add = ('U' == 1)) let Inst{19-16} = shift{16-13}; // Rn let Inst{15-12} = Rt; @@ -1020,6 +1021,7 @@ multiclass AI_str1<bit isByte, string opc, InstrItinClass iii, [(opnode GPR:$Rt, ldst_so_reg:$shift)]> { bits<4> Rt; bits<17> shift; + let shift{4} = 0; // Inst{4} = 0 let Inst{23} = shift{12}; // U (add = ('U' == 1)) let Inst{19-16} = shift{16-13}; // Rn let Inst{15-12} = Rt; diff --git a/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt b/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt new file mode 100644 index 0000000..23a0b85 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt @@ -0,0 +1,4 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# LDR (register) has encoding Inst{4} = 0. +0xba 0xae 0x9f 0x57 |