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authorAkira Hatanaka <ahatanaka@mips.com>2013-09-06 23:42:58 +0000
committerAkira Hatanaka <ahatanaka@mips.com>2013-09-06 23:42:58 +0000
commitcd3c1b9af9c79bd128a4811570269022a8183408 (patch)
treee2cf0d9fd5ed6f83d5307a0756cff7266698e4e4
parent1d04ca7987ef0abb5be07b11e3bb9c9e756a1fce (diff)
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[mips] Delete unused classes and defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190221 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/Mips/MipsInstrInfo.td10
1 files changed, 1 insertions, 9 deletions
diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index 83c7885..9fb2a75 100644
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -248,7 +248,7 @@ def brtarget : Operand<OtherVT> {
def calltarget : Operand<iPTR> {
let EncoderMethod = "getJumpTargetOpValue";
}
-def calltarget64: Operand<i64>;
+
def simm16 : Operand<i32> {
let DecoderMethod= "DecodeSimm16";
}
@@ -449,14 +449,6 @@ class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
let isReMaterializable = 1;
}
-class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
- InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> {
- bits<21> addr;
- let Inst{25-21} = addr{20-16};
- let Inst{15-0} = addr{15-0};
- let DecoderMethod = "DecodeMem";
-}
-
// Memory Load/Store
class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :