Fix Android.mk.

17 files changed, 62 insertions, 51 deletions

diff --git a/lib/Analysis/Android.mk b/lib/Analysis/Android.mk
index bd0f59c..aa4dcc0 100644
--- a/lib/Analysis/Android.mk
+++ b/lib/Analysis/Android.mk
@@ -8,6 +8,7 @@ analysis_SRC_FILES :=	\
 	AliasSetTracker.cpp	\
 	Analysis.cpp	\
 	BasicAliasAnalysis.cpp	\
+	BlockFrequency.cpp \
 	BranchProbabilityInfo.cpp \
 	CFGPrinter.cpp	\
 	CaptureTracking.cpp	\
diff --git a/lib/CodeGen/Android.mk b/lib/CodeGen/Android.mk
index 1cbf6cd..9daa0fd 100644
--- a/lib/CodeGen/Android.mk
+++ b/lib/CodeGen/Android.mk
@@ -60,7 +60,6 @@ codegen_SRC_FILES :=   \
 	Passes.cpp  \
 	PeepholeOptimizer.cpp	\
 	PostRASchedulerList.cpp \
-	PreAllocSplitting.cpp   \
 	ProcessImplicitDefs.cpp \
 	PrologEpilogInserter.cpp    \
 	PseudoSourceValue.cpp   \
@@ -71,6 +70,7 @@ codegen_SRC_FILES :=   \
 	RegAllocPBQP.cpp    \
 	RegisterCoalescer.cpp   \
 	RegisterClassInfo.cpp \
+	RegisterCoalescer.cpp \
 	RegisterScavenging.cpp  \
 	RenderMachineFunction.cpp	\
 	ScheduleDAG.cpp \
@@ -80,7 +80,6 @@ codegen_SRC_FILES :=   \
 	ScoreboardHazardRecognizer.cpp \
 	ShadowStackGC.cpp   \
 	ShrinkWrapping.cpp  \
-	SimpleRegisterCoalescing.cpp    \
 	SjLjEHPrepare.cpp   \
 	SlotIndexes.cpp \
 	Spiller.cpp \
diff --git a/lib/MC/Android.mk b/lib/MC/Android.mk
index a92df92..43062da 100644
--- a/lib/MC/Android.mk
+++ b/lib/MC/Android.mk
@@ -35,6 +35,7 @@ mc_SRC_FILES :=    \
 	MCWin64EH.cpp \
 	WinCOFFObjectWriter.cpp	\
 	WinCOFFStreamer.cpp	\
+	SubtargetFeature.cpp \
 	TargetAsmBackend.cpp
 
 # For the host
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index 7ed07c2..2afbb77 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -272,10 +272,10 @@ namespace {
 
     unsigned getHiLo16ImmOpValue(const MachineInstr &MI, unsigned Op)
       const {
-      const TargetInstrDesc &TID = MI.getDesc();
+      const MCInstrDesc &MCID = MI.getDesc();
       const MachineOperand &MO = MI.getOperand(Op);
 
-      unsigned Reloc = (TID.Opcode == ARM::MOVi16 ?
+      unsigned Reloc = (MCID.Opcode == ARM::MOVi16 ?
                        ARM::reloc_arm_movw : ARM::reloc_arm_movt);
 
       if (!MO.isImm()) {
@@ -803,7 +803,7 @@ void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
 
 void ARMCodeEmitter::emitLEApcrelInstruction(const MachineInstr &MI) {
   // It's basically add r, pc, (LCPI - $+8)
-  const TargetInstrDesc &TID = MI.getDesc();
+  const MCInstrDesc &MCID = MI.getDesc();
 
   unsigned Binary = 0;
 
@@ -811,7 +811,7 @@ void ARMCodeEmitter::emitLEApcrelInstruction(const MachineInstr &MI) {
   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
 
   // Encode S bit if MI modifies CPSR.
-  Binary |= getAddrModeSBit(MI, TID);
+  Binary |= getAddrModeSBit(MI, MCID);
 
   // Encode Rd.
   Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
@@ -1086,7 +1086,7 @@ void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
   // Part of binary is determined by TableGn.
   unsigned Binary = getBinaryCodeForInstr(MI);
 
-  if (TID.Opcode == ARM::MOVi16 || TID.Opcode == ARM::MOVTi16) {
+  if (MCID.Opcode == ARM::MOVi16 || MCID.Opcode == ARM::MOVTi16) {
       emitWordLE(Binary);
       return;
   }
@@ -1359,7 +1359,7 @@ void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
   // Part of binary is determined by TableGn.
   unsigned Binary = getBinaryCodeForInstr(MI);
 
-  if (TID.getOpcode() == ARM::LDMIA_RET) {
+  if (MCID.getOpcode() == ARM::LDMIA_RET) {
     IsUpdating = true;
     Binary |= 0x8B00000;
   }
@@ -1571,7 +1571,7 @@ void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
   // Part of binary is determined by TableGn.
   unsigned Binary = getBinaryCodeForInstr(MI);
 
-  if (TID.Opcode == ARM::B) {
+  if (MCID.Opcode == ARM::B) {
     Binary = 0xEA000000;
   }
 
diff --git a/lib/Target/ARM/Android.mk b/lib/Target/ARM/Android.mk
index 1223599..91d84cc 100644
--- a/lib/Target/ARM/Android.mk
+++ b/lib/Target/ARM/Android.mk
@@ -3,10 +3,7 @@ LOCAL_PATH := $(call my-dir)
 arm_codegen_TBLGEN_TABLES :=	\
 	ARMGenAsmWriter.inc	\
 	ARMGenMCCodeEmitter.inc \
-	ARMGenRegisterInfo.h.inc\
-	ARMGenRegisterNames.inc	\
 	ARMGenRegisterInfo.inc	\
-	ARMGenInstrNames.inc	\
 	ARMGenInstrInfo.inc	\
 	ARMGenDAGISel.inc	\
 	ARMGenFastISel.inc	\
diff --git a/lib/Target/ARM/AsmParser/Android.mk b/lib/Target/ARM/AsmParser/Android.mk
index 552dedd..664de6c 100644
--- a/lib/Target/ARM/AsmParser/Android.mk
+++ b/lib/Target/ARM/AsmParser/Android.mk
@@ -6,9 +6,8 @@ include $(CLEAR_VARS)
 include $(CLEAR_TBLGEN_VARS)
 
 TBLGEN_TABLES :=	\
-	ARMGenInstrNames.inc	\
-	ARMGenRegisterNames.inc	\
-	ARMGenRegisterInfo.h.inc \
+	ARMGenInstrInfo.inc	\
+	ARMGenRegisterInfo.inc \
 	ARMGenAsmMatcher.inc
 
 
diff --git a/lib/Target/ARM/Disassembler/Android.mk b/lib/Target/ARM/Disassembler/Android.mk
index 0e3c32c..d5c9c7b 100644
--- a/lib/Target/ARM/Disassembler/Android.mk
+++ b/lib/Target/ARM/Disassembler/Android.mk
@@ -3,10 +3,8 @@ LOCAL_PATH := $(call my-dir)
 arm_disassembler_TBLGEN_TABLES := \
     ARMGenDecoderTables.inc \
     ARMGenEDInfo.inc \
-    ARMGenInstrNames.inc \
     ARMGenInstrInfo.inc \
-    ARMGenRegisterNames.inc \
-    ARMGenRegisterInfo.h.inc
+    ARMGenRegisterInfo.inc
 
 arm_disassembler_SRC_FILES := \
     ARMDisassembler.cpp \
diff --git a/lib/Target/ARM/InstPrinter/Android.mk b/lib/Target/ARM/InstPrinter/Android.mk
index 3a35023..5ecad8b 100644
--- a/lib/Target/ARM/InstPrinter/Android.mk
+++ b/lib/Target/ARM/InstPrinter/Android.mk
@@ -2,8 +2,8 @@ LOCAL_PATH := $(call my-dir)
 
 arm_asm_printer_TBLGEN_TABLES :=    \
     ARMGenAsmWriter.inc \
-    ARMGenRegisterNames.inc\
-    ARMGenInstrNames.inc
+    ARMGenRegisterInfo.inc\
+    ARMGenInstrInfo.inc
 
 arm_asm_printer_SRC_FILES :=    \
     ARMInstPrinter.cpp
diff --git a/lib/Target/ARM/TargetInfo/Android.mk b/lib/Target/ARM/TargetInfo/Android.mk
index e07da39..a03fff9 100644
--- a/lib/Target/ARM/TargetInfo/Android.mk
+++ b/lib/Target/ARM/TargetInfo/Android.mk
@@ -1,8 +1,8 @@
 LOCAL_PATH := $(call my-dir)
 
 arm_target_info_TBLGEN_TABLES :=	\
-	ARMGenRegisterNames.inc	\
-	ARMGenInstrNames.inc
+	ARMGenRegisterInfo.inc	\
+	ARMGenInstrInfo.inc
 
 arm_target_info_SRC_FILES :=	\
 	ARMTargetInfo.cpp
diff --git a/lib/Target/Android.mk b/lib/Target/Android.mk
index 09a33ad..1c668d8 100644
--- a/lib/Target/Android.mk
+++ b/lib/Target/Android.mk
@@ -2,7 +2,6 @@ LOCAL_PATH:= $(call my-dir)
 
 target_SRC_FILES :=	\
 	Mangler.cpp	\
-	SubtargetFeature.cpp	\
 	Target.cpp	\
 	TargetAsmInfo.cpp	\
 	TargetAsmLexer.cpp	\
diff --git a/lib/Target/X86/Android.mk b/lib/Target/X86/Android.mk
index d0e5334..3e95a31 100644
--- a/lib/Target/X86/Android.mk
+++ b/lib/Target/X86/Android.mk
@@ -3,10 +3,7 @@ LOCAL_PATH := $(call my-dir)
 x86_codegen_TBLGEN_TABLES :=	\
     X86GenAsmWriter.inc \
     X86GenAsmWriter1.inc \
-    X86GenRegisterInfo.h.inc	\
-    X86GenRegisterNames.inc	\
     X86GenRegisterInfo.inc	\
-    X86GenInstrNames.inc	\
     X86GenInstrInfo.inc	\
     X86GenDAGISel.inc	\
     X86GenFastISel.inc	\
diff --git a/lib/Target/X86/AsmParser/Android.mk b/lib/Target/X86/AsmParser/Android.mk
index 00b06c4..faeaae6 100644
--- a/lib/Target/X86/AsmParser/Android.mk
+++ b/lib/Target/X86/AsmParser/Android.mk
@@ -7,8 +7,8 @@ include $(CLEAR_TBLGEN_VARS)
 
 TBLGEN_TABLES :=	\
 	X86GenAsmMatcher.inc	\
-	X86GenInstrNames.inc	\
-	X86GenRegisterNames.inc
+	X86GenInstrInfo.inc	\
+	X86GenRegisterInfo.inc
 
 
 TBLGEN_TD_DIR := $(LOCAL_PATH)/..
diff --git a/lib/Target/X86/Disassembler/Android.mk b/lib/Target/X86/Disassembler/Android.mk
index 0c65722..69d3435 100644
--- a/lib/Target/X86/Disassembler/Android.mk
+++ b/lib/Target/X86/Disassembler/Android.mk
@@ -3,7 +3,7 @@ LOCAL_PATH := $(call my-dir)
 x86_disassembler_TBLGEN_TABLES := \
 	X86GenDisassemblerTables.inc	\
 	X86GenEDInfo.inc	\
-	X86GenRegisterNames.inc
+	X86GenRegisterInfo.inc
 
 x86_disassembler_SRC_FILES := \
 	X86Disassembler.cpp	\
diff --git a/lib/Target/X86/InstPrinter/Android.mk b/lib/Target/X86/InstPrinter/Android.mk
index 6f14bcd..11c9244 100644
--- a/lib/Target/X86/InstPrinter/Android.mk
+++ b/lib/Target/X86/InstPrinter/Android.mk
@@ -3,9 +3,8 @@ LOCAL_PATH := $(call my-dir)
 x86_instprinter_TBLGEN_TABLES := \
   X86GenAsmWriter.inc \
   X86GenAsmWriter1.inc \
-  X86GenInstrNames.inc \
-  X86GenRegisterNames.inc \
-  X86GenRegisterInfo.h.inc
+  X86GenInstrInfo.inc \
+  X86GenRegisterInfo.inc
 
 x86_instprinter_SRC_FILES := \
   X86ATTInstPrinter.cpp \
diff --git a/lib/Target/X86/MCTargetDesc/Android.mk b/lib/Target/X86/MCTargetDesc/Android.mk
new file mode 100644
index 0000000..70b88f8
--- /dev/null
+++ b/lib/Target/X86/MCTargetDesc/Android.mk
@@ -0,0 +1,36 @@
+#LOCAL_PATH := $(call my-dir)
+#
+#x86_codegen_SRC_FILES :=	\
+#	X86TargetDesc.cpp
+#
+## For the host
+## =====================================================
+#include $(CLEAR_VARS)
+#include $(CLEAR_TBLGEN_VARS)
+#
+#TBLGEN_TABLES := $(x86_codegen_TBLGEN_TABLES)
+#
+#LOCAL_SRC_FILES := $(x86_codegen_SRC_FILES)
+#
+#LOCAL_MODULE:= libLLVMX86Desc
+#
+#LOCAL_MODULE_TAGS := optional
+#
+#include $(LLVM_HOST_BUILD_MK)
+#include $(BUILD_HOST_STATIC_LIBRARY)
+#
+## For the device only
+## =====================================================
+#ifeq ($(TARGET_ARCH),x86)
+#include $(CLEAR_VARS)
+#include $(CLEAR_TBLGEN_VARS)
+#
+#LOCAL_SRC_FILES := $(x86_codegen_SRC_FILES)
+#
+#LOCAL_MODULE:= libLLVMX86Desc
+#
+#LOCAL_MODULE_TAGS := optional
+#
+#include $(LLVM_DEVICE_BUILD_MK)
+#include $(BUILD_STATIC_LIBRARY)
+#endif
diff --git a/lib/Target/X86/TargetInfo/Android.mk b/lib/Target/X86/TargetInfo/Android.mk
index 4c99807..5d81f33 100644
--- a/lib/Target/X86/TargetInfo/Android.mk
+++ b/lib/Target/X86/TargetInfo/Android.mk
@@ -1,8 +1,8 @@
 LOCAL_PATH := $(call my-dir)
 
 x86_target_info_TBLGEN_TABLES :=	\
-	X86GenRegisterNames.inc	\
-	X86GenInstrNames.inc
+	X86GenRegisterInfo.inc	\
+	X86GenInstrInfo.inc
 
 x86_target_info_SRC_FILES :=	\
 	X86TargetInfo.cpp
diff --git a/llvm-tblgen-rules.mk b/llvm-tblgen-rules.mk
index 79d1b0a..3da6950 100644
--- a/llvm-tblgen-rules.mk
+++ b/llvm-tblgen-rules.mk
@@ -28,29 +28,14 @@ ifneq ($(TBLGEN_TD_DIR),)
 tblgen_source_dir := $(TBLGEN_TD_DIR)
 endif
 
-ifneq ($(filter %GenRegisterNames.inc,$(tblgen_gen_tables)),)
-$(intermediates)/%GenRegisterNames.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
-	$(call transform-td-to-out,register-enums)
-endif
-
-ifneq ($(filter %GenRegisterInfo.h.inc,$(tblgen_gen_tables)),)
-$(intermediates)/%GenRegisterInfo.h.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
-	$(call transform-td-to-out,register-desc-header)
-endif
-
 ifneq ($(filter %GenRegisterInfo.inc,$(tblgen_gen_tables)),)
 $(intermediates)/%GenRegisterInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
-	$(call transform-td-to-out,register-desc)
-endif
-
-ifneq ($(filter %GenInstrNames.inc,$(tblgen_gen_tables)),)
-$(intermediates)/%GenInstrNames.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
-	$(call transform-td-to-out,instr-enums)
+	$(call transform-td-to-out,register-info)
 endif
 
 ifneq ($(filter %GenInstrInfo.inc,$(tblgen_gen_tables)),)
 $(intermediates)/%GenInstrInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
-	$(call transform-td-to-out,instr-desc)
+	$(call transform-td-to-out,instr-info)
 endif
 
 ifneq ($(filter %GenAsmWriter.inc,$(tblgen_gen_tables)),)