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| author | Robert Wilhelm <robert.wilhelm@gmx.net> | 2013-09-28 13:42:22 +0000 |
|---|---|---|
| committer | Robert Wilhelm <robert.wilhelm@gmx.net> | 2013-09-28 13:42:22 +0000 |
| commit | 3f4f420ab7acb10221ba971543a7eed5489fb626 (patch) | |
| tree | d5b748cdf5567c17cb13fc823a5d7bc6ec9814e0 /include/llvm/Target | |
| parent | f80a63fa23862e578de919f4b44d4fcdee68fd0d (diff) | |
| download | external_llvm-3f4f420ab7acb10221ba971543a7eed5489fb626.zip external_llvm-3f4f420ab7acb10221ba971543a7eed5489fb626.tar.gz external_llvm-3f4f420ab7acb10221ba971543a7eed5489fb626.tar.bz2 | |
Even more spelling fixes for "instruction".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191611 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/Target')
| -rw-r--r-- | include/llvm/Target/TargetSchedule.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/llvm/Target/TargetSchedule.td b/include/llvm/Target/TargetSchedule.td index e81a2fb..9d4858a 100644 --- a/include/llvm/Target/TargetSchedule.td +++ b/include/llvm/Target/TargetSchedule.td @@ -76,7 +76,7 @@ def instregex; // See MCSchedule.h for detailed comments. class SchedMachineModel { int IssueWidth = -1; // Max micro-ops that may be scheduled per cycle. - int MinLatency = -1; // Determines which instrucions are allowed in a group. + int MinLatency = -1; // Determines which instructions are allowed in a group. // (-1) inorder (0) ooo, (1): inorder +var latencies. int MicroOpBufferSize = -1; // Max micro-ops that can be buffered. int LoadLatency = -1; // Cycles for loads to access the cache. |