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authorDan Gohman <gohman@apple.com>2009-09-25 22:26:13 +0000
committerDan Gohman <gohman@apple.com>2009-09-25 22:26:13 +0000
commit2bf0649e053d1589689d2e4cf32c7bf1e5e6ae12 (patch)
treef0f224b0c81e02a0b5ffb8f68ebfa89ce645e01c /lib/CodeGen/LiveIntervalAnalysis.cpp
parent29438d13e036cb454b2089b8e175fc93f62bbba2 (diff)
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Simplify a few more uses of reg_iterator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82812 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/LiveIntervalAnalysis.cpp')
-rw-r--r--lib/CodeGen/LiveIntervalAnalysis.cpp6
1 files changed, 2 insertions, 4 deletions
diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index e1b23fd..be78200 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -1087,11 +1087,9 @@ LiveIntervals::isProfitableToCoalesce(LiveInterval &DstInt, LiveInterval &SrcInt
SmallVector<MachineInstr*,16> &OtherCopies) {
bool HaveConflict = false;
unsigned NumIdent = 0;
- for (MachineRegisterInfo::reg_iterator ri = mri_->reg_begin(SrcInt.reg),
- re = mri_->reg_end(); ri != re; ++ri) {
+ for (MachineRegisterInfo::def_iterator ri = mri_->def_begin(SrcInt.reg),
+ re = mri_->def_end(); ri != re; ++ri) {
MachineOperand &O = ri.getOperand();
- if (!O.isDef())
- continue;
MachineInstr *MI = &*ri;
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;