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| author | Craig Topper <craig.topper@gmail.com> | 2012-03-05 05:37:41 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2012-03-05 05:37:41 +0000 |
| commit | 9ebfbf8b9fd5f982e0db9293808bd32168615ba9 (patch) | |
| tree | 77ce098c0d4851df8117d3d0e669b8580911a98f /lib/CodeGen/PostRASchedulerList.cpp | |
| parent | ec93b6decad4b95fd8a9531dc024b2b1881019bf (diff) | |
| download | external_llvm-9ebfbf8b9fd5f982e0db9293808bd32168615ba9.zip external_llvm-9ebfbf8b9fd5f982e0db9293808bd32168615ba9.tar.gz external_llvm-9ebfbf8b9fd5f982e0db9293808bd32168615ba9.tar.bz2 | |
Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce static data size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152016 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/PostRASchedulerList.cpp')
| -rw-r--r-- | lib/CodeGen/PostRASchedulerList.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp index 20ed8c5..e59aa9d 100644 --- a/lib/CodeGen/PostRASchedulerList.cpp +++ b/lib/CodeGen/PostRASchedulerList.cpp @@ -377,7 +377,7 @@ void SchedulePostRATDList::StartBlockForKills(MachineBasicBlock *BB) { unsigned Reg = *I; LiveRegs.set(Reg); // Repeat, for all subregs. - for (const unsigned *Subreg = TRI->getSubRegisters(Reg); + for (const uint16_t *Subreg = TRI->getSubRegisters(Reg); *Subreg; ++Subreg) LiveRegs.set(*Subreg); } @@ -391,7 +391,7 @@ void SchedulePostRATDList::StartBlockForKills(MachineBasicBlock *BB) { unsigned Reg = *I; LiveRegs.set(Reg); // Repeat, for all subregs. - for (const unsigned *Subreg = TRI->getSubRegisters(Reg); + for (const uint16_t *Subreg = TRI->getSubRegisters(Reg); *Subreg; ++Subreg) LiveRegs.set(*Subreg); } @@ -418,7 +418,7 @@ bool SchedulePostRATDList::ToggleKillFlag(MachineInstr *MI, MO.setIsKill(false); bool AllDead = true; const unsigned SuperReg = MO.getReg(); - for (const unsigned *Subreg = TRI->getSubRegisters(SuperReg); + for (const uint16_t *Subreg = TRI->getSubRegisters(SuperReg); *Subreg; ++Subreg) { if (LiveRegs.test(*Subreg)) { MI->addOperand(MachineOperand::CreateReg(*Subreg, @@ -471,7 +471,7 @@ void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) { LiveRegs.reset(Reg); // Repeat for all subregs. - for (const unsigned *Subreg = TRI->getSubRegisters(Reg); + for (const uint16_t *Subreg = TRI->getSubRegisters(Reg); *Subreg; ++Subreg) LiveRegs.reset(*Subreg); } @@ -490,7 +490,7 @@ void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) { if (!killedRegs.test(Reg)) { kill = true; // A register is not killed if any subregs are live... - for (const unsigned *Subreg = TRI->getSubRegisters(Reg); + for (const uint16_t *Subreg = TRI->getSubRegisters(Reg); *Subreg; ++Subreg) { if (LiveRegs.test(*Subreg)) { kill = false; @@ -524,7 +524,7 @@ void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) { LiveRegs.set(Reg); - for (const unsigned *Subreg = TRI->getSubRegisters(Reg); + for (const uint16_t *Subreg = TRI->getSubRegisters(Reg); *Subreg; ++Subreg) LiveRegs.set(*Subreg); } |