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path: root/lib/CodeGen/PostRASchedulerList.cpp
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* Update aosp/master LLVM for rebase to r235153Pirama Arumuga Nainar2015-05-181-1/+1
* Update aosp/master LLVM for rebase to r230699.Stephen Hines2015-03-231-3/+1
* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-021-24/+40
* Update LLVM for 3.5 rebase (r209712).Stephen Hines2014-05-291-11/+12
* Update to LLVM 3.5a.Stephen Hines2014-04-241-181/+62
* After PostRA scheduling, don't set kill flags on undef operands.Andrew Trick2013-10-161-2/+2
* mi-sched: Don't call MBB.size() in initSUnits. The driver already has instr c...Andrew Trick2013-08-231-7/+18
* Simplify logic now that r182490 is in place. No functional change intended.Chad Rosier2013-05-221-10/+8
* Remove special-casing of return blocks for liveness.Jakob Stoklund Olesen2013-02-051-19/+5
* Use MachineInstrBuilder in a few CodeGen passes.Jakob Stoklund Olesen2012-12-201-5/+3
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-11/+11
* misched: Don't consider artificial edges weak edges.Andrew Trick2012-11-131-1/+1
* misched: Infrastructure for weak DAG edges.Andrew Trick2012-11-121-7/+7
* Switch most getReservedRegs() clients to the MRI equivalent.Jakob Stoklund Olesen2012-10-151-3/+2
* Release build: guard dump functions withManman Ren2012-09-111-1/+1
* Release build: guard dump functions with "ifndef NDEBUG"Manman Ren2012-09-061-0/+2
* Add a getName function to MachineFunction. Use it in places that previously d...Craig Topper2012-08-221-1/+1
* Move RegisterClassInfo.h.Andrew Trick2012-06-061-1/+1
* Remove unused private fields found by clang's new -Wunused-private-field.Benjamin Kramer2012-06-061-1/+0
* Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen2012-06-011-19/+13
* This patch fixes a problem which arose when using the Post-RA schedulerPreston Gurd2012-04-231-0/+4
* misched interface: rename Begin/End to RegionBegin/RegionEnd since they are n...Andrew Trick2012-03-091-7/+7
* misched prep: Expose the ScheduleDAGInstrs interface so targets mayAndrew Trick2012-03-071-1/+1
* misched prep: rename InsertPos to End.Andrew Trick2012-03-071-8/+8
* misched preparation: rename core scheduler methods for consistency.Andrew Trick2012-03-071-17/+17
* misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.Andrew Trick2012-03-071-12/+38
* misched preparation: modularize schedule emission.Andrew Trick2012-03-071-0/+36
* misched preparation: modularize schedule printing.Andrew Trick2012-03-071-0/+18
* misched preparation: modularize schedule verification.Andrew Trick2012-03-071-2/+8
* Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce stati...Craig Topper2012-03-051-6/+6
* BitVectorize loop.Benjamin Kramer2012-02-231-3/+1
* post-ra-sched: Turn the KillIndices vector into a bitvector, it only stored t...Benjamin Kramer2012-02-231-28/+22
* post-ra-sched: Replace a std::set of regs with a bitvector.Benjamin Kramer2012-02-231-5/+4
* Make calls scheduling boundaries post-ra.Jakob Stoklund Olesen2012-02-231-1/+4
* Handle regmasks in FixupKills.Jakob Stoklund Olesen2012-02-231-0/+4
* Make all pointers to TargetRegisterClass const since they are all pointers to...Craig Topper2012-02-221-3/+3
* Codegen pass definition cleanup. No functionality.Andrew Trick2012-02-081-12/+5
* Move pass configuration out of pass constructors: PostRAScheduler.Andrew Trick2012-02-081-6/+8
* misched: Added ScheduleDAGInstrs::IsPostRAAndrew Trick2012-01-141-1/+1
* - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a functionEvan Cheng2011-12-141-1/+4
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-1/+1
* Remove all remaining uses of Value::getNameStr().Benjamin Kramer2011-11-151-2/+2
* Rename TargetSubtarget to TargetSubtargetInfo for consistency.Evan Cheng2011-07-011-12/+13
* Teach antidependency breakers to use RegisterClassInfo.Jakob Stoklund Olesen2011-06-161-5/+10
* Update DBG_VALUEs while breaking anti dependencies.Devang Patel2011-06-021-1/+1
* Add an issue width check to the postRA scheduler. Patch by Max Kazakov!Andrew Trick2011-06-011-0/+6
* Typo: Reviewed by Alistair.Andrew Trick2011-05-061-1/+1
* Post-RA scheduler compile time fix. Quadratic computation of DAG node depth.Andrew Trick2011-05-061-4/+10
* Various bits of framework needed for precise machine-level selectionAndrew Trick2010-12-241-37/+37
* Teach if-converter to be more careful with predicating instructions that wouldEvan Cheng2010-09-101-1/+1