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| author | Evan Cheng <evan.cheng@apple.com> | 2012-02-23 01:19:06 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2012-02-23 01:19:06 +0000 |
| commit | c892aeb26601cc5109490d30c7e170cb07f84428 (patch) | |
| tree | ca73ce26498fc637a12d4d57cdcb3632b4334793 /lib/CodeGen/PostRASchedulerList.cpp | |
| parent | bbad2f1040fea671b4413f53b3fd816cb7bd2443 (diff) | |
| download | external_llvm-c892aeb26601cc5109490d30c7e170cb07f84428.zip external_llvm-c892aeb26601cc5109490d30c7e170cb07f84428.tar.gz external_llvm-c892aeb26601cc5109490d30c7e170cb07f84428.tar.bz2 | |
Optimize a couple of common patterns involving conditional moves where the false
value is zero. Instead of a cmov + op, issue an conditional op instead. e.g.
cmp r9, r4
mov r4, #0
moveq r4, #1
orr lr, lr, r4
should be:
cmp r9, r4
orreq lr, lr, #1
That is, optimize (or x, (cmov 0, y, cond)) to (or.cond x, y). Similarly extend
this to xor as well as (and x, (cmov -1, y, cond)) => (and.cond x, y).
It's possible to extend this to ADD and SUB but I don't think they are common.
rdar://8659097
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151224 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/PostRASchedulerList.cpp')
0 files changed, 0 insertions, 0 deletions