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authorDan Gohman <gohman@apple.com>2010-11-09 01:54:35 +0000
committerDan Gohman <gohman@apple.com>2010-11-09 01:54:35 +0000
commit6a559cd6959bef28d20acef2129e5510bcc12bb8 (patch)
tree46cbdb94111f9f9d13a07eb18b71de8dcabf8a18 /lib/CodeGen/SelectionDAG/DAGCombiner.cpp
parentbe7c5116a754b4c539b4e385006452af13fe6df1 (diff)
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Fix DAGCombiner to avoid folding a sext-in-reg or similar through a shl
in order to fold it into a load. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118471 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/DAGCombiner.cpp')
-rw-r--r--lib/CodeGen/SelectionDAG/DAGCombiner.cpp1
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 7154d9d..1a0f503 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -4120,6 +4120,7 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
// we can fold the truncate through the shift.
unsigned ShLeftAmt = 0;
if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
+ ExtVT == VT &&
TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
ShLeftAmt = N01->getZExtValue();