LegalizeTypes support for VSETCC. Fixes PR2575.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53938 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 38 insertions, 9 deletions

diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 8122459..644bb10 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -418,6 +418,7 @@ private:
   SDOperand ScalarizeVecRes_SELECT(SDNode *N);
   SDOperand ScalarizeVecRes_UNDEF(SDNode *N);
   SDOperand ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N);
+  SDOperand ScalarizeVecRes_VSETCC(SDNode *N);
 
   // Vector Operand Scalarization: <1 x ty> -> ty.
   bool ScalarizeVectorOperand(SDNode *N, unsigned OpNo);
@@ -434,19 +435,19 @@ private:
 
   // Vector Result Splitting: <128 x ty> -> 2 x <64 x ty>.
   void SplitVectorResult(SDNode *N, unsigned OpNo);
+  void SplitVecRes_BinOp(SDNode *N, SDOperand &Lo, SDOperand &Hi);
+  void SplitVecRes_UnOp(SDNode *N, SDOperand &Lo, SDOperand &Hi);
 
-  void SplitVecRes_UNDEF(SDNode *N, SDOperand &Lo, SDOperand &Hi);
-  void SplitVecRes_LOAD(LoadSDNode *N, SDOperand &Lo, SDOperand &Hi);
+  void SplitVecRes_BIT_CONVERT(SDNode *N, SDOperand &Lo, SDOperand &Hi);
   void SplitVecRes_BUILD_PAIR(SDNode *N, SDOperand &Lo, SDOperand &Hi);
-  void SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDOperand &Lo, SDOperand &Hi);
-  void SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDOperand &Lo, SDOperand &Hi);
-
   void SplitVecRes_BUILD_VECTOR(SDNode *N, SDOperand &Lo, SDOperand &Hi);
   void SplitVecRes_CONCAT_VECTORS(SDNode *N, SDOperand &Lo, SDOperand &Hi);
-  void SplitVecRes_BIT_CONVERT(SDNode *N, SDOperand &Lo, SDOperand &Hi);
-  void SplitVecRes_UnOp(SDNode *N, SDOperand &Lo, SDOperand &Hi);
-  void SplitVecRes_BinOp(SDNode *N, SDOperand &Lo, SDOperand &Hi);
   void SplitVecRes_FPOWI(SDNode *N, SDOperand &Lo, SDOperand &Hi);
+  void SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDOperand &Lo, SDOperand &Hi);
+  void SplitVecRes_LOAD(LoadSDNode *N, SDOperand &Lo, SDOperand &Hi);
+  void SplitVecRes_UNDEF(SDNode *N, SDOperand &Lo, SDOperand &Hi);
+  void SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDOperand &Lo, SDOperand &Hi);
+  void SplitVecRes_VSETCC(SDNode *N, SDOperand &Lo, SDOperand &Hi);
 
   // Vector Operand Splitting: <128 x ty> -> 2 x <64 x ty>.
   bool SplitVectorOperand(SDNode *N, unsigned OpNo);
diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 9f6f3e7..f0875fa 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -46,9 +46,10 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
   case ISD::FPOWI:          R = ScalarizeVecRes_FPOWI(N); break;
   case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
   case ISD::LOAD:           R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
-  case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
   case ISD::SELECT:         R = ScalarizeVecRes_SELECT(N); break;
   case ISD::UNDEF:          R = ScalarizeVecRes_UNDEF(N); break;
+  case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
+  case ISD::VSETCC:         R = ScalarizeVecRes_VSETCC(N); break;
 
   case ISD::ADD:
   case ISD::FADD:
@@ -141,6 +142,19 @@ SDOperand DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
   return GetScalarizedVector(N->getOperand(Op));
 }
 
+SDOperand DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
+  MVT NewVT = N->getValueType(0).getVectorElementType();
+  SDOperand LHS = GetScalarizedVector(N->getOperand(0));
+  SDOperand RHS = GetScalarizedVector(N->getOperand(1));
+  LHS = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, RHS,
+                    N->getOperand(2));
+  return
+    DAG.getNode(ISD::SELECT, NewVT, LHS,
+                DAG.getConstant(APInt::getAllOnesValue(NewVT.getSizeInBits()),
+                                NewVT),
+                DAG.getConstant(0ULL, NewVT));
+}
+
 
 //===----------------------------------------------------------------------===//
 //  Operand Vector Scalarization <1 x ty> -> ty.
@@ -251,6 +265,7 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
   case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
   case ISD::LOAD:           SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);break;
   case ISD::VECTOR_SHUFFLE: SplitVecRes_VECTOR_SHUFFLE(N, Lo, Hi); break;
+  case ISD::VSETCC:         SplitVecRes_VSETCC(N, Lo, Hi); break;
 
   case ISD::CTTZ:
   case ISD::CTLZ:
@@ -520,6 +535,19 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDOperand &Lo,
   Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &Ops[0], Ops.size());
 }
 
+void DAGTypeLegalizer::SplitVecRes_VSETCC(SDNode *N, SDOperand &Lo,
+                                          SDOperand &Hi) {
+  MVT LoVT, HiVT;
+  GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
+
+  SDOperand LL, LH, RL, RH;
+  GetSplitVector(N->getOperand(0), LL, LH);
+  GetSplitVector(N->getOperand(1), RL, RH);
+
+  Lo = DAG.getNode(ISD::VSETCC, LoVT, LL, RL, N->getOperand(2));
+  Hi = DAG.getNode(ISD::VSETCC, HiVT, LH, RH, N->getOperand(2));
+}
+
 
 //===----------------------------------------------------------------------===//
 //  Operand Vector Splitting