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author | Evan Cheng <evan.cheng@apple.com> | 2008-10-17 06:16:07 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2008-10-17 06:16:07 +0000 |
commit | 6784598895c184889b82a9d213c307c70b1ea444 (patch) | |
tree | d83b8c190c0bd441b7035c9398f79bc21bc4da9d /lib/CodeGen/VirtRegMap.cpp | |
parent | abec474236601d7c10469a212decd010727ba060 (diff) | |
download | external_llvm-6784598895c184889b82a9d213c307c70b1ea444.zip external_llvm-6784598895c184889b82a9d213c307c70b1ea444.tar.gz external_llvm-6784598895c184889b82a9d213c307c70b1ea444.tar.bz2 |
Fix a very subtle spiller bug: UpdateKills should not forget to track defs of aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57673 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/VirtRegMap.cpp')
-rw-r--r-- | lib/CodeGen/VirtRegMap.cpp | 22 |
1 files changed, 14 insertions, 8 deletions
diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp index 1c3c139..79857d9 100644 --- a/lib/CodeGen/VirtRegMap.cpp +++ b/lib/CodeGen/VirtRegMap.cpp @@ -635,7 +635,8 @@ static bool InvalidateRegDef(MachineBasicBlock::iterator I, /// marked kill, then it must be due to register reuse. Transfer the kill info /// over. static void UpdateKills(MachineInstr &MI, BitVector &RegKills, - std::vector<MachineOperand*> &KillOps) { + std::vector<MachineOperand*> &KillOps, + const TargetRegisterInfo* TRI) { const TargetInstrDesc &TID = MI.getDesc(); for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { MachineOperand &MO = MI.getOperand(i); @@ -669,6 +670,11 @@ static void UpdateKills(MachineInstr &MI, BitVector &RegKills, unsigned Reg = MO.getReg(); RegKills.reset(Reg); KillOps[Reg] = NULL; + // It also defines (or partially define) aliases. + for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) { + RegKills.reset(*AS); + KillOps[*AS] = NULL; + } } } @@ -839,7 +845,7 @@ namespace { Spills.addAvailable(NewOp.StackSlotOrReMat, MI, NewPhysReg); --MII; - UpdateKills(*MII, RegKills, KillOps); + UpdateKills(*MII, RegKills, KillOps, TRI); DOUT << '\t' << *MII; DOUT << "Reuse undone!\n"; @@ -1283,7 +1289,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { } // This invalidates Phys. Spills.ClobberPhysReg(Phys); - UpdateKills(*prior(MII), RegKills, KillOps); + UpdateKills(*prior(MII), RegKills, KillOps, TRI); DOUT << '\t' << *prior(MII); } } @@ -1500,7 +1506,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { TII->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC); MachineInstr *CopyMI = prior(MII); - UpdateKills(*CopyMI, RegKills, KillOps); + UpdateKills(*CopyMI, RegKills, KillOps, TRI); // This invalidates DesignatedReg. Spills.ClobberPhysReg(DesignatedReg); @@ -1550,7 +1556,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { MI.getOperand(i).setIsKill(); unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; MI.getOperand(i).setReg(RReg); - UpdateKills(*prior(MII), RegKills, KillOps); + UpdateKills(*prior(MII), RegKills, KillOps, TRI); DOUT << '\t' << *prior(MII); } @@ -1650,7 +1656,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { // super-register is needed below. if (KillOpnd && !KillOpnd->getSubReg() && TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, true,NewMIs)){ - MBB.insert(MII, NewMIs[0]); + MBB.insert(MII, NewMIs[0]); NewStore = NewMIs[1]; MBB.insert(MII, NewStore); VRM.addSpillSlotUse(SS, NewStore); @@ -1825,7 +1831,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { VRM.RemoveMachineInstrFromMaps(&MI); MBB.erase(&MI); Erased = true; - UpdateKills(*LastStore, RegKills, KillOps); + UpdateKills(*LastStore, RegKills, KillOps, TRI); goto ProcessNextInst; } } @@ -1835,7 +1841,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { DistanceMap.insert(std::make_pair(&MI, Dist++)); if (!Erased && !BackTracked) { for (MachineBasicBlock::iterator II = &MI; II != NextMII; ++II) - UpdateKills(*II, RegKills, KillOps); + UpdateKills(*II, RegKills, KillOps, TRI); } MII = NextMII; } |