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author | Bill Wendling <isanbard@gmail.com> | 2009-01-30 23:03:19 +0000 |
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committer | Bill Wendling <isanbard@gmail.com> | 2009-01-30 23:03:19 +0000 |
commit | 7581bfa2757a3149c6d17c0fe592e5c3808aa843 (patch) | |
tree | aa4421e3289933230b386bf830923af82743f9bf /lib/CodeGen | |
parent | a03e74bf6795478fd0b8d8d09b86ab517cda84b5 (diff) | |
download | external_llvm-7581bfa2757a3149c6d17c0fe592e5c3808aa843.zip external_llvm-7581bfa2757a3149c6d17c0fe592e5c3808aa843.tar.gz external_llvm-7581bfa2757a3149c6d17c0fe592e5c3808aa843.tar.bz2 |
Get rid of the non-DebugLoc-ified getNOT() method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63442 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
-rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 8 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 8 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 15 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/TargetLowering.cpp | 10 |
4 files changed, 14 insertions, 27 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 8eae470..604432b 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -2845,15 +2845,15 @@ SDValue DAGCombiner::visitSELECT(SDNode *N) { } // fold (select C, 0, X) -> (and (not C), X) if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { - SDValue NOTNode = DAG.getNOT(N0, VT); + SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); AddToWorkList(NOTNode.getNode()); - return DAG.getNode(ISD::AND, VT, NOTNode, N2); + return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); } // fold (select C, X, 1) -> (or (not C), X) if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); AddToWorkList(NOTNode.getNode()); - return DAG.getNode(ISD::OR, VT, NOTNode, N1); + return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); } // fold (select C, X, 0) -> (and C, X) if (VT == MVT::i1 && N2C && N2C->isNullValue()) @@ -5739,7 +5739,7 @@ SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1, if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { SDValue NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), N0); - SDValue NotN0 = DAG.getNOT(N0, XType); + SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); return DAG.getNode(ISD::SRL, XType, DAG.getNode(ISD::AND, XType, NegN0, NotN0), DAG.getConstant(XType.getSizeInBits()-1, diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index eba252f..5ae6364 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -6321,7 +6321,7 @@ SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) { SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); } - Op = DAG.getNOT(Op, VT); + Op = DAG.getNOT(DebugLoc::getUnknownLoc(), Op, VT); return DAG.getNode(ISD::CTPOP, VT, Op); } case ISD::CTTZ: { @@ -6330,8 +6330,10 @@ SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) { // { return 32 - nlz(~x & (x-1)); } // see also http://www.hackersdelight.org/HDcode/ntz.cc MVT VT = Op.getValueType(); - SDValue Tmp3 = DAG.getNode(ISD::AND, VT, DAG.getNOT(Op, VT), - DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); + SDValue Tmp3 = DAG.getNode(ISD::AND, VT, + DAG.getNOT(DebugLoc::getUnknownLoc(), Op, VT), + DAG.getNode(ISD::SUB, VT, Op, + DAG.getConstant(1, VT))); // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) && TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index d3a59b4..bb1c728 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -841,21 +841,6 @@ SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT VT) { /// getNOT - Create a bitwise NOT operation as (XOR Val, -1). /// -SDValue SelectionDAG::getNOT(SDValue Val, MVT VT) { - SDValue NegOne; - if (VT.isVector()) { - MVT EltVT = VT.getVectorElementType(); - SDValue NegOneElt = getConstant(EltVT.getIntegerVTBitMask(), EltVT); - std::vector<SDValue> NegOnes(VT.getVectorNumElements(), NegOneElt); - NegOne = getNode(ISD::BUILD_VECTOR, VT, &NegOnes[0], NegOnes.size()); - } else - NegOne = getConstant(VT.getIntegerVTBitMask(), VT); - - return getNode(ISD::XOR, VT, Val, NegOne); -} - -/// getNOT - Create a bitwise NOT operation as (XOR Val, -1). -/// SDValue SelectionDAG::getNOT(DebugLoc DL, SDValue Val, MVT VT) { SDValue NegOne; if (VT.isVector()) { diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 1f9d9cf..ebc5067 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -1841,7 +1841,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1, default: assert(0 && "Unknown integer setcc!"); case ISD::SETEQ: // X == Y -> ~(X^Y) Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); - N0 = DAG.getNOT(Temp, MVT::i1); + N0 = DAG.getNOT(DebugLoc::getUnknownLoc(), Temp, MVT::i1); if (!DCI.isCalledByLegalizer()) DCI.AddToWorklist(Temp.getNode()); break; @@ -1850,28 +1850,28 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1, break; case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y - Temp = DAG.getNOT(N0, MVT::i1); + Temp = DAG.getNOT(DebugLoc::getUnknownLoc(), N0, MVT::i1); N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); if (!DCI.isCalledByLegalizer()) DCI.AddToWorklist(Temp.getNode()); break; case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X - Temp = DAG.getNOT(N1, MVT::i1); + Temp = DAG.getNOT(DebugLoc::getUnknownLoc(), N1, MVT::i1); N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); if (!DCI.isCalledByLegalizer()) DCI.AddToWorklist(Temp.getNode()); break; case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y - Temp = DAG.getNOT(N0, MVT::i1); + Temp = DAG.getNOT(DebugLoc::getUnknownLoc(), N0, MVT::i1); N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); if (!DCI.isCalledByLegalizer()) DCI.AddToWorklist(Temp.getNode()); break; case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X - Temp = DAG.getNOT(N1, MVT::i1); + Temp = DAG.getNOT(DebugLoc::getUnknownLoc(), N1, MVT::i1); N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); break; } |