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author | Jiangning Liu <jiangning.liu@arm.com> | 2013-11-06 02:25:49 +0000 |
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committer | Jiangning Liu <jiangning.liu@arm.com> | 2013-11-06 02:25:49 +0000 |
commit | 258115258f8fe15e9d74b5fb524f90b75bb917d1 (patch) | |
tree | f7df585491dc8c3376135fb0e8d39db4dd0b643a /lib/Target/AArch64/AArch64InstrFormats.td | |
parent | 10bb82e54fc0608e6220581bda0405af8f12d32f (diff) | |
download | external_llvm-258115258f8fe15e9d74b5fb524f90b75bb917d1.zip external_llvm-258115258f8fe15e9d74b5fb524f90b75bb917d1.tar.gz external_llvm-258115258f8fe15e9d74b5fb524f90b75bb917d1.tar.bz2 |
Implement AArch64 Neon instruction set Bitwise Extract.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194118 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64/AArch64InstrFormats.td')
-rw-r--r-- | lib/Target/AArch64/AArch64InstrFormats.td | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/lib/Target/AArch64/AArch64InstrFormats.td b/lib/Target/AArch64/AArch64InstrFormats.td index b3e114a..8a21426 100644 --- a/lib/Target/AArch64/AArch64InstrFormats.td +++ b/lib/Target/AArch64/AArch64InstrFormats.td @@ -983,6 +983,24 @@ class NeonInstAlias<string Asm, dag Result, bit Emit = 0b1> : InstAlias<Asm, Result, Emit> { } +// Format AdvSIMD bitwise extract +class NeonI_BitExtract<bit q, bits<2> op2, + dag outs, dag ins, string asmstr, + list<dag> patterns, InstrItinClass itin> + : A64InstRdnm<outs, ins, asmstr, patterns, itin> { + let Inst{31} = 0b0; + let Inst{30} = q; + let Inst{29-24} = 0b101110; + let Inst{23-22} = op2; + let Inst{21} = 0b0; + // Inherit Rm in 20-16 + let Inst{15} = 0b0; + // imm4 in 14-11 + let Inst{10} = 0b0; + // Inherit Rn in 9-5 + // Inherit Rd in 4-0 +} + // Format AdvSIMD 3 vector registers with same vector type class NeonI_3VSame<bit q, bit u, bits<2> size, bits<5> opcode, dag outs, dag ins, string asmstr, |