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| author | Jiangning Liu <jiangning.liu@arm.com> | 2013-09-09 02:20:27 +0000 |
|---|---|---|
| committer | Jiangning Liu <jiangning.liu@arm.com> | 2013-09-09 02:20:27 +0000 |
| commit | 959cd8f49bb85c8dfe971eb5a8a648ff41ca8ebd (patch) | |
| tree | 746a5fdf146ee7373e073b6c7b163147e7a693d4 /lib/Target/AArch64/AArch64InstrFormats.td | |
| parent | 56736c18c14e89a386dae969e33a31ce685a0a1c (diff) | |
| download | external_llvm-959cd8f49bb85c8dfe971eb5a8a648ff41ca8ebd.zip external_llvm-959cd8f49bb85c8dfe971eb5a8a648ff41ca8ebd.tar.gz external_llvm-959cd8f49bb85c8dfe971eb5a8a648ff41ca8ebd.tar.bz2 | |
Implement aarch64 neon instruction set AdvSIMD (3V Diff), covering the following 26 instructions,
SADDL, UADDL, SADDW, UADDW, SSUBL, USUBL, SSUBW, USUBW, ADDHN, RADDHN, SABAL, UABAL, SUBHN, RSUBHN, SABDL, UABDL, SMLAL, UMLAL, SMLSL, UMLSL, SQDMLAL, SQDMLSL, SMULL, UMULL, SQDMULL, PMULL
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190288 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64/AArch64InstrFormats.td')
| -rw-r--r-- | lib/Target/AArch64/AArch64InstrFormats.td | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/lib/Target/AArch64/AArch64InstrFormats.td b/lib/Target/AArch64/AArch64InstrFormats.td index 020ee6c..dd35367 100644 --- a/lib/Target/AArch64/AArch64InstrFormats.td +++ b/lib/Target/AArch64/AArch64InstrFormats.td @@ -990,6 +990,26 @@ class NeonI_3VSame<bit q, bit u, bits<2> size, bits<5> opcode, // Inherit Rd in 4-0 } +// Format AdvSIMD 3 vector registers with different vector type +class NeonI_3VDiff<bit q, bit u, bits<2> size, bits<4> opcode, + dag outs, dag ins, string asmstr, + list<dag> patterns, InstrItinClass itin> + : A64InstRdnm<outs, ins, asmstr, patterns, itin> +{ + let Inst{31} = 0b0; + let Inst{30} = q; + let Inst{29} = u; + let Inst{28-24} = 0b01110; + let Inst{23-22} = size; + let Inst{21} = 0b1; + // Inherit Rm in 20-16 + let Inst{15-12} = opcode; + let Inst{11} = 0b0; + let Inst{10} = 0b0; + // Inherit Rn in 9-5 + // Inherit Rd in 4-0 +} + // Format AdvSIMD 1 vector register with modified immediate class NeonI_1VModImm<bit q, bit op, dag outs, dag ins, string asmstr, |