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authorAmara Emerson <amara.emerson@arm.com>2013-10-31 09:32:11 +0000
committerAmara Emerson <amara.emerson@arm.com>2013-10-31 09:32:11 +0000
commitc2884320feebc543d2ce51151d5418dfc18da9e4 (patch)
tree0741cd0182a73f25f8f852c90a8b7751323dc4ef /lib/Target/AArch64/AArch64InstrFormats.td
parent0f5e68e3dc64e7dde41577649ad44b4453859276 (diff)
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[AArch64] Make the use of FP instructions optional, but enabled by default.
This adds a new subtarget feature called FPARMv8 (implied by NEON), and predicates the support of the FP instructions and registers on this feature. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193739 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/AArch64/AArch64InstrFormats.td')
-rw-r--r--lib/Target/AArch64/AArch64InstrFormats.td4
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/Target/AArch64/AArch64InstrFormats.td b/lib/Target/AArch64/AArch64InstrFormats.td
index d69db31..7a41ce0 100644
--- a/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/lib/Target/AArch64/AArch64InstrFormats.td
@@ -383,6 +383,8 @@ class A64I_extract<bit sf, bits<3> op, bit n,
// Inherits Rd in 4-0
}
+let Predicates = [HasFPARMv8] in {
+
// Format for floating-point compare instructions.
class A64I_fpcmp<bit m, bit s, bits<2> type, bits<2> op, bits<5> opcode2,
dag outs, dag ins, string asmstr,
@@ -562,6 +564,8 @@ class A64I_fpimm<bit m, bit s, bits<2> type, bits<5> imm5,
// Inherit Rd in 4-0
}
+}
+
// Format for load-register (literal) instructions.
class A64I_LDRlit<bits<2> opc, bit v,
dag outs, dag ins, string asmstr,