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author | Jim Grosbach <grosbach@apple.com> | 2010-08-19 17:52:13 +0000 |
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committer | Jim Grosbach <grosbach@apple.com> | 2010-08-19 17:52:13 +0000 |
commit | 74d7b0af58951dce2f874c600a6a48a2454b4914 (patch) | |
tree | 08ba331d307a8bcfe468e7a3604877dfa97a4fa8 /lib/Target/ARM/ARMBaseRegisterInfo.cpp | |
parent | c546c754597cdc99b2dfa70b4a1054575daa753a (diff) | |
download | external_llvm-74d7b0af58951dce2f874c600a6a48a2454b4914.zip external_llvm-74d7b0af58951dce2f874c600a6a48a2454b4914.tar.gz external_llvm-74d7b0af58951dce2f874c600a6a48a2454b4914.tar.bz2 |
Add Thumb1 support for virtual frame indices.
rdar://8277890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111533 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMBaseRegisterInfo.cpp')
-rw-r--r-- | lib/Target/ARM/ARMBaseRegisterInfo.cpp | 28 |
1 files changed, 15 insertions, 13 deletions
diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index 0330fac..ef316a5 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -1385,13 +1385,6 @@ needsFrameBaseReg(MachineInstr *MI, unsigned operand) const { // FIXME: For testing, return true for all loads/stores and false for // everything else. We want to create lots of base regs to shake out bugs. - // - // FIXME: This is Thumb2/ARM only for now to keep it simpler. - ARMFunctionInfo *AFI = - MI->getParent()->getParent()->getInfo<ARMFunctionInfo>(); - if (AFI->isThumb1OnlyFunction()) - return false; - unsigned Opc = MI->getOpcode(); switch (Opc) { @@ -1401,6 +1394,7 @@ needsFrameBaseReg(MachineInstr *MI, unsigned operand) const { case ARM::t2STRi12: case ARM::t2STRi8: case ARM::VLDRS: case ARM::VLDRD: case ARM::VSTRS: case ARM::VSTRD: + case ARM::tSTRspi: case ARM::tLDRspi: return true; default: return false; @@ -1414,14 +1408,14 @@ materializeFrameBaseRegister(MachineBasicBlock::iterator I, unsigned BaseReg, int FrameIdx) const { ARMFunctionInfo *AFI = I->getParent()->getParent()->getInfo<ARMFunctionInfo>(); - unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri; - assert(!AFI->isThumb1OnlyFunction() && - "This materializeFrameBaseRegister does not support Thumb1!"); + unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : + (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri); MachineInstrBuilder MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), TII.get(ADDriOpc), BaseReg) .addFrameIndex(FrameIdx).addImm(0); - AddDefaultCC(AddDefaultPred(MIB)); + if (!AFI->isThumb1OnlyFunction()) + AddDefaultCC(AddDefaultPred(MIB)); } void @@ -1469,13 +1463,14 @@ bool ARMBaseRegisterInfo::isBaseRegInRange(const MachineInstr *MI, unsigned NumBits = 0; unsigned Scale = 1; unsigned ImmIdx = 0; - int InstrOffs; + int InstrOffs = 0;; switch(AddrMode) { case ARMII::AddrModeT2_i8: case ARMII::AddrModeT2_i12: // i8 supports only negative, and i12 supports only positive, so // based on Offset sign, consider the appropriate instruction - Offset += MI->getOperand(i+1).getImm(); + InstrOffs = MI->getOperand(i+1).getImm(); + Scale = 1; if (Offset < 0) { NumBits = 8; Offset = -Offset; @@ -1509,6 +1504,13 @@ bool ARMBaseRegisterInfo::isBaseRegInRange(const MachineInstr *MI, NumBits = 8; break; } + case ARMII::AddrModeT1_s: { + ImmIdx = i+1; + InstrOffs = MI->getOperand(ImmIdx).getImm(); + NumBits = 5; + Scale = 4; + break; + } default: llvm_unreachable("Unsupported addressing mode!"); break; |