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| author | Jim Grosbach <grosbach@apple.com> | 2011-12-20 00:59:38 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-12-20 00:59:38 +0000 |
| commit | 04b5d93250bef585631a583a85f6733b1bdc8c52 (patch) | |
| tree | 946b0eac66d3cf78fa40f2a13c56b139cf5c5d62 /lib/Target/ARM/AsmParser | |
| parent | ea93373a0a1bf1d087f5414e566384c2af3ebf09 (diff) | |
| download | external_llvm-04b5d93250bef585631a583a85f6733b1bdc8c52.zip external_llvm-04b5d93250bef585631a583a85f6733b1bdc8c52.tar.gz external_llvm-04b5d93250bef585631a583a85f6733b1bdc8c52.tar.bz2 | |
ARM assembly shifts by zero should be plain 'mov' instructions.
"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.
rdar://10604663
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146937 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/AsmParser')
| -rw-r--r-- | lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 9852cc8..ac7532b 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -5945,6 +5945,23 @@ processInstruction(MCInst &Inst, } break; } + case ARM::MOVsi: { + ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm()); + if (SOpc == ARM_AM::rrx) return false; + if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) { + // Shifting by zero is accepted as a vanilla 'MOVr' + MCInst TmpInst; + TmpInst.setOpcode(ARM::MOVr); + TmpInst.addOperand(Inst.getOperand(0)); + TmpInst.addOperand(Inst.getOperand(1)); + TmpInst.addOperand(Inst.getOperand(3)); + TmpInst.addOperand(Inst.getOperand(4)); + TmpInst.addOperand(Inst.getOperand(5)); + Inst = TmpInst; + return true; + } + return false; + } case ARM::t2IT: { // The mask bits for all but the first condition are represented as // the low bit of the condition code value implies 't'. We currently |