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author | Sylvestre Ledru <sylvestre@debian.org> | 2012-09-27 10:14:43 +0000 |
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committer | Sylvestre Ledru <sylvestre@debian.org> | 2012-09-27 10:14:43 +0000 |
commit | 94c22716d60ff5edf6a98a3c67e0faa001be1142 (patch) | |
tree | 2442b2b9658c29e72b1dd7abae926751854c68dc /lib/Target/ARM/AsmParser | |
parent | 7e2c793a2b5c746344652b6579e958ee42fafdcc (diff) | |
download | external_llvm-94c22716d60ff5edf6a98a3c67e0faa001be1142.zip external_llvm-94c22716d60ff5edf6a98a3c67e0faa001be1142.tar.gz external_llvm-94c22716d60ff5edf6a98a3c67e0faa001be1142.tar.bz2 |
Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164768 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/AsmParser')
-rw-r--r-- | lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index a16931e..aa5ba46 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -5316,7 +5316,7 @@ validateInstruction(MCInst &Inst, // instruction. We'll make the transformation in processInstruction() // if necessary. // - // Thumb LDM instructions are writeback if the base register is not + // Thumb LDM instructions are writeback iff the base register is not // in the register list. unsigned Rn = Inst.getOperand(0).getReg(); bool hasWritebackToken = @@ -7023,7 +7023,7 @@ processInstruction(MCInst &Inst, Inst.addOperand(MCOperand::CreateReg(0)); // cc_out break; case ARM::tADDi8: - // If the immediate is in the range 0-7, we want tADDi3 if Rd was + // If the immediate is in the range 0-7, we want tADDi3 iff Rd was // explicitly specified. From the ARM ARM: "Encoding T1 is preferred // to encoding T2 if <Rd> is specified and encoding T2 is preferred // to encoding T1 if <Rd> is omitted." @@ -7033,7 +7033,7 @@ processInstruction(MCInst &Inst, } break; case ARM::tSUBi8: - // If the immediate is in the range 0-7, we want tADDi3 if Rd was + // If the immediate is in the range 0-7, we want tADDi3 iff Rd was // explicitly specified. From the ARM ARM: "Encoding T1 is preferred // to encoding T2 if <Rd> is specified and encoding T2 is preferred // to encoding T1 if <Rd> is omitted." |