diff options
author | Anton Korobeynikov <asl@math.spbu.ru> | 2009-05-03 13:05:22 +0000 |
---|---|---|
committer | Anton Korobeynikov <asl@math.spbu.ru> | 2009-05-03 13:05:22 +0000 |
commit | cf9adf2cbb8298e83b53d7bee2ddab4c875cb3c5 (patch) | |
tree | 3852b9a4c9d29baabe21e52e43e9149bc3ab0eab /lib/Target/MSP430/MSP430RegisterInfo.td | |
parent | 0fc32dae8f380f57087bf48e4248f1ad3326a1b0 (diff) | |
download | external_llvm-cf9adf2cbb8298e83b53d7bee2ddab4c875cb3c5.zip external_llvm-cf9adf2cbb8298e83b53d7bee2ddab4c875cb3c5.tar.gz external_llvm-cf9adf2cbb8298e83b53d7bee2ddab4c875cb3c5.tar.bz2 |
Add 8-bit regclass and pattern for sext_inreg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70721 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/MSP430/MSP430RegisterInfo.td')
-rw-r--r-- | lib/Target/MSP430/MSP430RegisterInfo.td | 93 |
1 files changed, 73 insertions, 20 deletions
diff --git a/lib/Target/MSP430/MSP430RegisterInfo.td b/lib/Target/MSP430/MSP430RegisterInfo.td index cc17e32..7564402 100644 --- a/lib/Target/MSP430/MSP430RegisterInfo.td +++ b/lib/Target/MSP430/MSP430RegisterInfo.td @@ -16,37 +16,90 @@ class MSP430Reg<bits<4> num, string n> : Register<n> { let Namespace = "MSP430"; } +class MSP430RegWithSubregs<bits<4> num, string n, list<Register> subregs> + : RegisterWithSubRegs<n, subregs> { + field bits<4> Num = num; + let Namespace = "MSP430"; +} + //===----------------------------------------------------------------------===// // Registers //===----------------------------------------------------------------------===// -def PC : MSP430Reg<0, "r0">; -def SP : MSP430Reg<1, "r1">; -def SR : MSP430Reg<2, "r2">; -def CG : MSP430Reg<3, "r3">; -def FP : MSP430Reg<4, "r4">; -def R5 : MSP430Reg<5, "r5">; -def R6 : MSP430Reg<6, "r6">; -def R7 : MSP430Reg<7, "r7">; -def R8 : MSP430Reg<8, "r8">; -def R9 : MSP430Reg<9, "r9">; -def R10 : MSP430Reg<10, "r10">; -def R11 : MSP430Reg<11, "r11">; -def R12 : MSP430Reg<12, "r12">; -def R13 : MSP430Reg<13, "r13">; -def R14 : MSP430Reg<14, "r14">; -def R15 : MSP430Reg<15, "r15">; +def PCB : MSP430Reg<0, "r0">; +def SPB : MSP430Reg<1, "r1">; +def SRB : MSP430Reg<2, "r2">; +def CGB : MSP430Reg<3, "r3">; +def FPB : MSP430Reg<4, "r4">; +def R5B : MSP430Reg<5, "r5">; +def R6B : MSP430Reg<6, "r6">; +def R7B : MSP430Reg<7, "r7">; +def R8B : MSP430Reg<8, "r8">; +def R9B : MSP430Reg<9, "r9">; +def R10B : MSP430Reg<10, "r10">; +def R11B : MSP430Reg<11, "r11">; +def R12B : MSP430Reg<12, "r12">; +def R13B : MSP430Reg<13, "r13">; +def R14B : MSP430Reg<14, "r14">; +def R15B : MSP430Reg<15, "r15">; -// FIXME: we need subregs & special handling for 8 bit stuff +def PCW : MSP430RegWithSubregs<0, "r0", [PCB]>; +def SPW : MSP430RegWithSubregs<1, "r1", [SPB]>; +def SRW : MSP430RegWithSubregs<2, "r2", [SRB]>; +def CGW : MSP430RegWithSubregs<3, "r3", [CGB]>; +def FPW : MSP430RegWithSubregs<4, "r4", [FPB]>; +def R5W : MSP430RegWithSubregs<5, "r5", [R5B]>; +def R6W : MSP430RegWithSubregs<6, "r6", [R6B]>; +def R7W : MSP430RegWithSubregs<7, "r7", [R7B]>; +def R8W : MSP430RegWithSubregs<8, "r8", [R8B]>; +def R9W : MSP430RegWithSubregs<9, "r9", [R9B]>; +def R10W : MSP430RegWithSubregs<10, "r10", [R10B]>; +def R11W : MSP430RegWithSubregs<11, "r11", [R11B]>; +def R12W : MSP430RegWithSubregs<12, "r12", [R12B]>; +def R13W : MSP430RegWithSubregs<13, "r13", [R13B]>; +def R14W : MSP430RegWithSubregs<14, "r14", [R14B]>; +def R15W : MSP430RegWithSubregs<15, "r15", [R15B]>; + +def : SubRegSet<1, [PCW, SPW, SRW, CGW, FPW, + R5W, R6W, R7W, R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W], + [PCB, SPB, SRB, CGB, FPB, + R5B, R6B, R7B, R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>; + +def GR8 : RegisterClass<"MSP430", [i8], 8, + // Volatile registers + [R12B, R13B, R14B, R15B, R11B, R10B, R9B, R8B, R7B, R6B, R5B, + // Frame pointer, sometimes allocable + FPB, + // Volatile, but not allocable + PCB, SPB, SRB, CGB]> +{ + let MethodProtos = [{ + iterator allocation_order_end(const MachineFunction &MF) const; + }]; + let MethodBodies = [{ + GR8Class::iterator + GR8Class::allocation_order_end(const MachineFunction &MF) const { + const TargetMachine &TM = MF.getTarget(); + const TargetRegisterInfo *RI = TM.getRegisterInfo(); + // Depending on whether the function uses frame pointer or not, last 5 or 4 + // registers on the list above are reserved + if (RI->hasFP(MF)) + return end()-5; + else + return end()-4; + } + }]; +} def GR16 : RegisterClass<"MSP430", [i16], 16, // Volatile registers - [R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5, + [R12W, R13W, R14W, R15W, R11W, R10W, R9W, R8W, R7W, R6W, R5W, // Frame pointer, sometimes allocable - FP, + FPW, // Volatile, but not allocable - PC, SP, SR, CG]> + PCW, SPW, SRW, CGW]> { + let SubRegClassList = [GR8]; let MethodProtos = [{ iterator allocation_order_end(const MachineFunction &MF) const; }]; |