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| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-03-29 19:17:42 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-03-29 19:17:42 +0000 |
| commit | 5114226c1896f250be8881adf67d55a7e54b50fc (patch) | |
| tree | 864ab74576a53000854484b62fd87ba319a1b698 /lib/Target/Mips/MipsSERegisterInfo.cpp | |
| parent | bc4de7cec1b87fd84e6dad2c512c927d67967a22 (diff) | |
| download | external_llvm-5114226c1896f250be8881adf67d55a7e54b50fc.zip external_llvm-5114226c1896f250be8881adf67d55a7e54b50fc.tar.gz external_llvm-5114226c1896f250be8881adf67d55a7e54b50fc.tar.bz2 | |
[mips] Define a function which returns the GPR register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178359 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsSERegisterInfo.cpp')
| -rw-r--r-- | lib/Target/Mips/MipsSERegisterInfo.cpp | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsSERegisterInfo.cpp b/lib/Target/Mips/MipsSERegisterInfo.cpp index a39b393..9696738 100644 --- a/lib/Target/Mips/MipsSERegisterInfo.cpp +++ b/lib/Target/Mips/MipsSERegisterInfo.cpp @@ -54,6 +54,15 @@ requiresFrameIndexScavenging(const MachineFunction &MF) const { return true; } +const TargetRegisterClass * +MipsSERegisterInfo::intRegClass(unsigned Size) const { + if (Size == 4) + return &Mips::CPURegsRegClass; + + assert(Size == 8); + return &Mips::CPU64RegsRegClass; +} + void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo, int FrameIndex, uint64_t StackSize, |