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| author | Christian Konig <christian.koenig@amd.com> | 2013-02-16 11:28:22 +0000 |
|---|---|---|
| committer | Christian Konig <christian.koenig@amd.com> | 2013-02-16 11:28:22 +0000 |
| commit | e25e490793241e471036c3e2f969ce6a068e5ce1 (patch) | |
| tree | 3a45cc748382fb881432d9993e1e03e5ce28514d /lib/Target/R600/SIRegisterInfo.td | |
| parent | 8e4eebcecf291386a321d0f8582b8a57841ea8c9 (diff) | |
| download | external_llvm-e25e490793241e471036c3e2f969ce6a068e5ce1.zip external_llvm-e25e490793241e471036c3e2f969ce6a068e5ce1.tar.gz external_llvm-e25e490793241e471036c3e2f969ce6a068e5ce1.tar.bz2 | |
R600/SI: cleanup literal handling v3
Seems to be allot simpler, and also paves the
way for further improvements.
v2: rebased on master, use 0 in BUFFER_LOAD_FORMAT_XYZW,
use VGPR0 in dummy EXP, avoid compiler warning, break
after encoding the first literal.
v3: correctly use V_ADD_F32_e64
This is a candidate for the stable branch.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175354 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/R600/SIRegisterInfo.td')
| -rw-r--r-- | lib/Target/R600/SIRegisterInfo.td | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/lib/Target/R600/SIRegisterInfo.td b/lib/Target/R600/SIRegisterInfo.td index 150c92e..7f1fec0 100644 --- a/lib/Target/R600/SIRegisterInfo.td +++ b/lib/Target/R600/SIRegisterInfo.td @@ -22,8 +22,6 @@ def EXEC_LO : SIReg <"EXEC LO", 126>; def EXEC_HI : SIReg <"EXEC HI", 127>; def EXEC : SI_64<"EXEC", [EXEC_LO, EXEC_HI], 126>; def SCC : SIReg<"SCC", 253>; -def SREG_LIT_0 : SIReg <"S LIT 0", 128>; -def SI_LITERAL_CONSTANT : SIReg<"LITERAL CONSTANT", 255>; def M0 : SIReg <"M0", 124>; //Interpolation registers @@ -136,7 +134,7 @@ def VGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7, // Register class for all scalar registers (SGPRs + Special Registers) def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32, - (add SGPR_32, SREG_LIT_0, M0, EXEC_LO, EXEC_HI) + (add SGPR_32, M0, EXEC_LO, EXEC_HI) >; def SReg_64 : RegisterClass<"AMDGPU", [i64], 64, (add SGPR_64, VCC, EXEC)>; |