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| author | Preston Gurd <preston.gurd@intel.com> | 2013-04-25 20:29:37 +0000 |
|---|---|---|
| committer | Preston Gurd <preston.gurd@intel.com> | 2013-04-25 20:29:37 +0000 |
| commit | d6ac8e9a03d8fa7115079d86192bc4529e8281aa (patch) | |
| tree | 9553fbaac5e6badb3c220a49e83147e96b44c70f /lib/Target/X86/X86.td | |
| parent | 975b1ddf60387139357c8cbbaeb613de5a39294f (diff) | |
| download | external_llvm-d6ac8e9a03d8fa7115079d86192bc4529e8281aa.zip external_llvm-d6ac8e9a03d8fa7115079d86192bc4529e8281aa.tar.gz external_llvm-d6ac8e9a03d8fa7115079d86192bc4529e8281aa.tar.bz2 | |
This patch adds the X86FixupLEAs pass, which will reduce instruction
latency for certain models of the Intel Atom family, by converting
instructions into their equivalent LEA instructions, when it is both
useful and possible to do so.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180573 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86.td')
| -rw-r--r-- | lib/Target/X86/X86.td | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/lib/Target/X86/X86.td b/lib/Target/X86/X86.td index 306e3ac..87bb68d 100644 --- a/lib/Target/X86/X86.td +++ b/lib/Target/X86/X86.td @@ -139,6 +139,8 @@ def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions", def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect", "CallRegIndirect", "true", "Call register indirect">; +def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true", + "LEA instruction needs inputs at AG stage">; //===----------------------------------------------------------------------===// // X86 processors supported. @@ -188,6 +190,7 @@ def : ProcessorModel<"atom", AtomModel, FeatureMOVBE, FeatureSlowBTMem, FeatureLeaForSP, FeatureSlowDivide, FeatureCallRegIndirect, + FeatureLEAUsesAG, FeaturePadShortFunctions]>; // "Arrandale" along with corei3 and corei5 |