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* Update aosp/master LLVM for rebase to r235153Pirama Arumuga Nainar2015-05-181-11/+9
* Update aosp/master LLVM for rebase to r230699.Stephen Hines2015-03-231-73/+165
* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-021-14/+56
* Update LLVM for rebase to r212749.Stephen Hines2014-07-211-2/+5
* Update LLVM for 3.5 rebase (r209712).Stephen Hines2014-05-291-2/+25
* Update to LLVM 3.5a.Stephen Hines2014-04-241-21/+32
* X86: Add a description for AMD bdver3 aka Steamroller.Benjamin Kramer2013-11-041-0/+8
* Enabling 3DNow! prefetch instruction for a few AMD processors: bobcat, jaguar,Yunzhong Gao2013-10-161-6/+6
* Rename this feature to "cx16" to match gcc's flag name. Apparently these stringsNick Lewycky2013-10-051-1/+1
* Adding a feature flag to the llvm backend for x86 TBM instruction set.Yunzhong Gao2013-09-241-1/+4
* Remove unused code, which had been commented out.Preston Gurd2013-09-171-5/+0
* Make F16C feature flag imply AVX rather than just checking both at the patterns.Craig Topper2013-09-161-1/+2
* Adds support for Atom Silvermont (SLM) - -march=slmPreston Gurd2013-09-131-9/+15
* Partial support for Intel SHA Extensions (sha1rnds4)Ben Langmuir2013-09-121-0/+3
* X86: Add a description of the Intel Atom Silvermont CPU.Benjamin Kramer2013-08-301-0/+9
* Rename features to match what gcc and clang use.Rafael Espindola2013-08-231-3/+3
* Rename mattr names for AVX-512 to from avx-512 -> avx512f, avx-512-pfi -> av5...Craig Topper2013-08-211-4/+4
* Added encoding prefixes for KNL instructions (EVEX).Elena Demikhovsky2013-07-281-3/+6
* I'm starting to commit KNL backend. I'll push patches one-by-one. This patch ...Elena Demikhovsky2013-07-241-0/+19
* X86: Add target description for btver2; make autodetection logic aware of AVX.Benjamin Kramer2013-05-031-1/+6
* This patch adds the X86FixupLEAs pass, which will reduce instructionPreston Gurd2013-04-251-0/+3
* [asm parser] Add support for predicating MnemonicAlias based on the assemblerChad Rosier2013-04-181-0/+6
* Add support of RDSEED defined in AVX2 extensionMichael Liao2013-03-281-0/+2
* Add the Haswell machine model.Nadav Rotem2013-03-281-1/+1
* For the current Atom processor, the fastest way to handle a callPreston Gurd2013-03-271-1/+6
* Add HLE target featureMichael Liao2013-03-261-1/+4
* Enable SandyBridgeModel for all modern Intel P6 descendants.Jakob Stoklund Olesen2013-03-261-34/+43
* Add PREFETCHW codegen supportMichael Liao2013-03-261-0/+2
* added basic support for Intel ADX instructionsKay Tiong Khoo2013-02-141-0/+2
* Pad Short Functions for Intel AtomPreston Gurd2013-01-081-3/+6
* Revert revision 171524. Original message:Nadav Rotem2013-01-051-6/+3
* The current Intel Atom microarchitecture has a feature whereby when a functionPreston Gurd2013-01-041-3/+6
* Make '-mtune=x86_64' assume fast unaligned memory accesses.Chandler Carruth2012-12-151-1/+2
* Revert "Make '-mtune=x86_64' assume fast unaligned memory accesses."Chandler Carruth2012-12-101-2/+1
* Make '-mtune=x86_64' assume fast unaligned memory accesses.Chandler Carruth2012-12-101-1/+2
* Address a FIXME and update the fast unaligned memory feature for newerChandler Carruth2012-12-101-7/+7
* Add support of RTM from TSX extensionMichael Liao2012-11-081-1/+4
* Atom has SIMD instruction set extension up to SSSE3Michael Liao2012-10-251-1/+1
* Fix 80-column violationCraig Topper2012-10-031-2/+2
* Add support for AMD Geode.Roman Divacky2012-09-121-0/+1
* Generic Bypass Slow DivPreston Gurd2012-09-041-1/+5
* Patch to enable FMA on bdver2 target. Make XOP feature enable FMA4 as well.Anitha Boyapati2012-08-161-2/+2
* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162010 91177308-0d34...Anitha Boyapati2012-08-161-2/+2
* I'm introducing a new machine model to simultaneously allow simpleAndrew Trick2012-07-071-2/+2
* Rename FMA3 feature flag to just FMA to match gcc so it can be added to clang.Craig Topper2012-06-031-2/+2
* X86: Rename the CLMUL target feature to PCLMUL.Benjamin Kramer2012-05-311-8/+8
* Make XOP and FMA4 require SSE4A to match GCC behavior. Use this to simplify B...Craig Topper2012-05-011-9/+8
* Make XOP imply AVX as its needed to legalize the registers types.Craig Topper2012-05-011-1/+2
* Make CLMUL and AES imply SSE2 since its needed to legalize the type.Craig Topper2012-05-011-2/+4
* Enable AVX and FMA4 for AMD Bulldozer processors.Craig Topper2012-05-011-5/+5
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