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* Update aosp/master LLVM for rebase to r235153Pirama Arumuga Nainar2015-05-181-11/+9
| | | | | Change-Id: I9bf53792f9fc30570e81a8d80d296c681d005ea7 (cherry picked from commit 0c7f116bb6950ef819323d855415b2f2b0aad987)
* Update aosp/master LLVM for rebase to r230699.Stephen Hines2015-03-231-73/+165
| | | | Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-021-14/+56
| | | | Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
* Update LLVM for rebase to r212749.Stephen Hines2014-07-211-2/+5
| | | | | | | Includes a cherry-pick of: r212948 - fixes a small issue with atomic calls Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
* Update LLVM for 3.5 rebase (r209712).Stephen Hines2014-05-291-2/+25
| | | | Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
* Update to LLVM 3.5a.Stephen Hines2014-04-241-21/+32
| | | | Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
* X86: Add a description for AMD bdver3 aka Steamroller.Benjamin Kramer2013-11-041-0/+8
| | | | | | This is just bdver2 + FSGSBase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193984 91177308-0d34-0410-b5e6-96231b3b80d8
* Enabling 3DNow! prefetch instruction for a few AMD processors: bobcat, jaguar,Yunzhong Gao2013-10-161-6/+6
| | | | | | | | | | | bulldozer and piledriver. Support for the instruction itself seems to have already been added in r178040. Differential Revision: http://llvm-reviews.chandlerc.com/D1933 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192828 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename this feature to "cx16" to match gcc's flag name. Apparently these stringsNick Lewycky2013-10-051-1/+1
| | | | | | | are directly tied to the flag names in clang with no remapping in between? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192044 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding a feature flag to the llvm backend for x86 TBM instruction set.Yunzhong Gao2013-09-241-1/+4
| | | | | | | | | | | | Adding TBM feature to bdver2 processor; piledriver supports this instruction set according to the following document: http://developer.amd.com/wordpress/media/2012/10/New-Bulldozer-and-Piledriver-Instructions.pdf Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1692 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191324 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused code, which had been commented out.Preston Gurd2013-09-171-5/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190869 91177308-0d34-0410-b5e6-96231b3b80d8
* Make F16C feature flag imply AVX rather than just checking both at the patterns.Craig Topper2013-09-161-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190775 91177308-0d34-0410-b5e6-96231b3b80d8
* Adds support for Atom Silvermont (SLM) - -march=slmPreston Gurd2013-09-131-9/+15
| | | | | | | | | | | | | | Implements Instruction scheduler latencies for Silvermont, using latencies from the Intel Silvermont Optimization Guide. Auto detects SLM. Turns on post RA scheduler when generating code for SLM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190717 91177308-0d34-0410-b5e6-96231b3b80d8
* Partial support for Intel SHA Extensions (sha1rnds4)Ben Langmuir2013-09-121-0/+3
| | | | | | | | | | Add basic assembly/disassembly support for the first Intel SHA instruction 'sha1rnds4'. Also includes feature flag, and test cases. Support for the remaining instructions will follow in a separate patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190611 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Add a description of the Intel Atom Silvermont CPU.Benjamin Kramer2013-08-301-0/+9
| | | | | | Currently this is just the atom model with SSE4.2 enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189669 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename features to match what gcc and clang use.Rafael Espindola2013-08-231-3/+3
| | | | | | | There is no advantage in being different and using the same names simplifies clang a bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189141 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename mattr names for AVX-512 to from avx-512 -> avx512f, avx-512-pfi -> ↵Craig Topper2013-08-211-4/+4
| | | | | | av512pf, avx-512-cdi -> avx512cd, avx-512-eri->avx512er. This matches better with official docs and what gcc patches appearto be using. I didn't touch the has* functions or the feature flag names to avoid change the td and lowering file while commits are still happening. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188859 91177308-0d34-0410-b5e6-96231b3b80d8
* Added encoding prefixes for KNL instructions (EVEX).Elena Demikhovsky2013-07-281-3/+6
| | | | | | | Added 512-bit operands printing. Added instruction formats for KNL instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187324 91177308-0d34-0410-b5e6-96231b3b80d8
* I'm starting to commit KNL backend. I'll push patches one-by-one. This patch ↵Elena Demikhovsky2013-07-241-0/+19
| | | | | | | | | includes support for the extended register set XMM16-31, YMM16-31, ZMM0-31. The full ISA you can see here: http://software.intel.com/en-us/intel-isa-extensions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187030 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Add target description for btver2; make autodetection logic aware of AVX.Benjamin Kramer2013-05-031-1/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181005 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch adds the X86FixupLEAs pass, which will reduce instructionPreston Gurd2013-04-251-0/+3
| | | | | | | | | | | latency for certain models of the Intel Atom family, by converting instructions into their equivalent LEA instructions, when it is both useful and possible to do so. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180573 91177308-0d34-0410-b5e6-96231b3b80d8
* [asm parser] Add support for predicating MnemonicAlias based on the assemblerChad Rosier2013-04-181-0/+6
| | | | | | | | | variant/dialect. Addresses a FIXME in the emitMnemonicAliases function. Use and test case to come shortly. rdar://13688439 and part of PR13340. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179804 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support of RDSEED defined in AVX2 extensionMichael Liao2013-03-281-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178314 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the Haswell machine model.Nadav Rotem2013-03-281-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178301 91177308-0d34-0410-b5e6-96231b3b80d8
* For the current Atom processor, the fastest way to handle a callPreston Gurd2013-03-271-1/+6
| | | | | | | | | | | | | | | indirect through a memory address is to load the memory address into a register and then call indirect through the register. This patch implements this improvement by modifying SelectionDAG to force a function address which is a memory reference to be loaded into a virtual register. Patch by Sriram Murali. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178171 91177308-0d34-0410-b5e6-96231b3b80d8
* Add HLE target featureMichael Liao2013-03-261-1/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178082 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable SandyBridgeModel for all modern Intel P6 descendants.Jakob Stoklund Olesen2013-03-261-34/+43
| | | | | | | | | | | | All Intel CPUs since Yonah look a lot alike, at least at the granularity of the scheduling models. We can add more accurate models for processors that aren't Sandy Bridge if required. Haswell will probably need its own. The Atom processor and anything based on NetBurst is completely different. So are the non-Intel chips. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178080 91177308-0d34-0410-b5e6-96231b3b80d8
* Add PREFETCHW codegen supportMichael Liao2013-03-261-0/+2
| | | | | | | | - Add 'PRFCHW' feature defined in AVX2 ISA extension git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178040 91177308-0d34-0410-b5e6-96231b3b80d8
* added basic support for Intel ADX instructionsKay Tiong Khoo2013-02-141-0/+2
| | | | | | -feature flag, instructions definitions, test cases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175196 91177308-0d34-0410-b5e6-96231b3b80d8
* Pad Short Functions for Intel AtomPreston Gurd2013-01-081-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | The current Intel Atom microarchitecture has a feature whereby when a function returns early then it is slightly faster to execute a sequence of NOP instructions to wait until the return address is ready, as opposed to simply stalling on the ret instruction until the return address is ready. When compiling for X86 Atom only, this patch will run a pass, called "X86PadShortFunction" which will add NOP instructions where less than four cycles elapse between function entry and return. It includes tests. This patch has been updated to address Nadav's review comments - Optimize only at >= O1 and don't do optimization if -Os is set - Stores MachineBasicBlock* instead of BBNum - Uses DenseMap instead of std::map - Fixes placement of braces Patch by Andy Zhang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171879 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert revision 171524. Original message:Nadav Rotem2013-01-051-6/+3
| | | | | | | | | | | | | | | | | | | | | | | URL: http://llvm.org/viewvc/llvm-project?rev=171524&view=rev Log: The current Intel Atom microarchitecture has a feature whereby when a function returns early then it is slightly faster to execute a sequence of NOP instructions to wait until the return address is ready, as opposed to simply stalling on the ret instruction until the return address is ready. When compiling for X86 Atom only, this patch will run a pass, called "X86PadShortFunction" which will add NOP instructions where less than four cycles elapse between function entry and return. It includes tests. Patch by Andy Zhang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171603 91177308-0d34-0410-b5e6-96231b3b80d8
* The current Intel Atom microarchitecture has a feature whereby when a functionPreston Gurd2013-01-041-3/+6
| | | | | | | | | | | | | | | | | | | returns early then it is slightly faster to execute a sequence of NOP instructions to wait until the return address is ready, as opposed to simply stalling on the ret instruction until the return address is ready. When compiling for X86 Atom only, this patch will run a pass, called "X86PadShortFunction" which will add NOP instructions where less than four cycles elapse between function entry and return. It includes tests. Patch by Andy Zhang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171524 91177308-0d34-0410-b5e6-96231b3b80d8
* Make '-mtune=x86_64' assume fast unaligned memory accesses.Chandler Carruth2012-12-151-1/+2
| | | | | | | | | | | | | | Not all chips targeted by x86_64 have this feature, but a dramatically increasing number do. Specifying a chip-specific tuning parameter will continue to turn the feature on or off as appropriate for that particular chip, but the generic flag should try to achieve the best performance on the most widely available hardware. Today, the number of chips with fast UA access dwarfs those without in the x86-64 space. Note that this also brings LLVM's code generation for this '-march' flag more in line with that of modern GCCs. Reviewed by Dan Gohman. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170269 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Make '-mtune=x86_64' assume fast unaligned memory accesses."Chandler Carruth2012-12-101-2/+1
| | | | | | Accidental commit... git svn betrayed me. Sorry for the noise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169741 91177308-0d34-0410-b5e6-96231b3b80d8
* Make '-mtune=x86_64' assume fast unaligned memory accesses.Chandler Carruth2012-12-101-1/+2
| | | | | | | | | | | | | | | | | | | Summary: Not all chips targeted by x86_64 have this feature, but a dramatically increasing number do. Specifying a chip-specific tuning parameter will continue to turn the feature on or off as appropriate for that particular chip, but the generic flag should try to achieve the best performance on the most widely available hardware. Today, the number of chips with fast UA access dwarfs those without in the x86-64 space. Note that this also brings LLVM's code generation for this '-march' flag more in line with that of modern GCCs. CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D195 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169740 91177308-0d34-0410-b5e6-96231b3b80d8
* Address a FIXME and update the fast unaligned memory feature for newerChandler Carruth2012-12-101-7/+7
| | | | | | | | | | | | | | | Intel chips. The model number rules were determined by inspecting Intel's documentation for their newer chip model numbers. My understanding is that all of the newer Intel chips have fast unaligned memory access, but if anyone is concerned about a particular chip, just shout. No tests updated; it's not clear we have dedicated tests for the chips' various features, but if anyone would like tests (or can point me at some existing ones), I'm happy to oblige. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169730 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support of RTM from TSX extensionMichael Liao2012-11-081-1/+4
| | | | | | | | | | - Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167573 91177308-0d34-0410-b5e6-96231b3b80d8
* Atom has SIMD instruction set extension up to SSSE3Michael Liao2012-10-251-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166665 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix 80-column violationCraig Topper2012-10-031-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165089 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for AMD Geode.Roman Divacky2012-09-121-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163710 91177308-0d34-0410-b5e6-96231b3b80d8
* Generic Bypass Slow DivPreston Gurd2012-09-041-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | - CodeGenPrepare pass for identifying div/rem ops - Backend specifies the type mapping using addBypassSlowDivType - Enabled only for Intel Atom with O2 32-bit -> 8-bit - Replace IDIV with instructions which test its value and use DIVB if the value is positive and less than 256. - In the case when the quotient and remainder of a divide are used a DIV and a REM instruction will be present in the IR. In the non-Atom case they are both lowered to IDIVs and CSE removes the redundant IDIV instruction, using the quotient and remainder from the first IDIV. However, due to this optimization CSE is not able to eliminate redundant IDIV instructions because they are located in different basic blocks. This is overcome by calculating both the quotient (DIV) and remainder (REM) in each basic block that is inserted by the optimization and reusing the result values when a subsequent DIV or REM instruction uses the same operands. - Test cases check for the presents of the optimization when calculating either the quotient, remainder, or both. Patch by Tyler Nowicki! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163150 91177308-0d34-0410-b5e6-96231b3b80d8
* Patch to enable FMA on bdver2 target. Make XOP feature enable FMA4 as well.Anitha Boyapati2012-08-161-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162012 91177308-0d34-0410-b5e6-96231b3b80d8
* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162010 ↵Anitha Boyapati2012-08-161-2/+2
| | | | 91177308-0d34-0410-b5e6-96231b3b80d8
* I'm introducing a new machine model to simultaneously allow simpleAndrew Trick2012-07-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename FMA3 feature flag to just FMA to match gcc so it can be added to clang.Craig Topper2012-06-031-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157903 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Rename the CLMUL target feature to PCLMUL.Benjamin Kramer2012-05-311-8/+8
| | | | | | | It was renamed in gcc/gas a while ago and causes all kinds of confusion because it was named differently in llvm and clang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157745 91177308-0d34-0410-b5e6-96231b3b80d8
* Make XOP and FMA4 require SSE4A to match GCC behavior. Use this to simplify ↵Craig Topper2012-05-011-9/+8
| | | | | | Bulldozer feature list. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155897 91177308-0d34-0410-b5e6-96231b3b80d8
* Make XOP imply AVX as its needed to legalize the registers types.Craig Topper2012-05-011-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155891 91177308-0d34-0410-b5e6-96231b3b80d8
* Make CLMUL and AES imply SSE2 since its needed to legalize the type.Craig Topper2012-05-011-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155888 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable AVX and FMA4 for AMD Bulldozer processors.Craig Topper2012-05-011-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155885 91177308-0d34-0410-b5e6-96231b3b80d8
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