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author | Chris Lattner <sabre@nondot.org> | 2010-06-05 04:17:30 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2010-06-05 04:17:30 +0000 |
commit | 1087f54ddb70bd2a7ab62608161e4a3f0c345935 (patch) | |
tree | dc95c8cba3a2dd08aa0facb0293c7689bca5e6bb /lib/Target/X86/X86InstrInfo.h | |
parent | 3eca98bb3ab1ec27ab8763298c416d282cdaa261 (diff) | |
download | external_llvm-1087f54ddb70bd2a7ab62608161e4a3f0c345935.zip external_llvm-1087f54ddb70bd2a7ab62608161e4a3f0c345935.tar.gz external_llvm-1087f54ddb70bd2a7ab62608161e4a3f0c345935.tar.bz2 |
revert r105521, which is breaking the buildbots with stuff like this:
In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105524 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrInfo.h')
-rw-r--r-- | lib/Target/X86/X86InstrInfo.h | 22 |
1 files changed, 4 insertions, 18 deletions
diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h index 9016c16..f5c8022 100644 --- a/lib/Target/X86/X86InstrInfo.h +++ b/lib/Target/X86/X86InstrInfo.h @@ -417,36 +417,22 @@ namespace X86II { OpcodeShift = 24, OpcodeMask = 0xFF << OpcodeShift - }; - // FIXME: The enum opcode space is over and more bits are needed. Anywhere - // those enums below are used, TSFlags must be shifted right by 32 first. - enum { - //===------------------------------------------------------------------===// - // VEX_4V - VEX prefixes are instruction prefixes used in AVX. - // VEX_4V is used to specify an additional AVX/SSE register. Several 2 - // address instructions in SSE are represented as 3 address ones in AVX - // and the additional register is encoded in VEX_VVVV prefix. - // - VEXShift = 0, - VEX_4V = 1 << VEXShift - }; - // getBaseOpcodeFor - This function returns the "base" X86 opcode for the // specified machine instruction. // - static inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) { + static inline unsigned char getBaseOpcodeFor(unsigned TSFlags) { return TSFlags >> X86II::OpcodeShift; } - static inline bool hasImm(uint64_t TSFlags) { + static inline bool hasImm(unsigned TSFlags) { return (TSFlags & X86II::ImmMask) != 0; } /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field /// of the specified instruction. - static inline unsigned getSizeOfImm(uint64_t TSFlags) { + static inline unsigned getSizeOfImm(unsigned TSFlags) { switch (TSFlags & X86II::ImmMask) { default: assert(0 && "Unknown immediate size"); case X86II::Imm8: @@ -460,7 +446,7 @@ namespace X86II { /// isImmPCRel - Return true if the immediate of the specified instruction's /// TSFlags indicates that it is pc relative. - static inline unsigned isImmPCRel(uint64_t TSFlags) { + static inline unsigned isImmPCRel(unsigned TSFlags) { switch (TSFlags & X86II::ImmMask) { default: assert(0 && "Unknown immediate size"); case X86II::Imm8PCRel: |