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authorAndrew Trick <atrick@apple.com>2012-06-05 03:44:29 +0000
committerAndrew Trick <atrick@apple.com>2012-06-05 03:44:29 +0000
commitd05b46115f5049b7b094d4049aa88f09f7d6b65a (patch)
tree35b2941580395ab98188cdce1a9fd5b7fafcc6e1 /lib/Target/X86/X86Schedule.td
parent76e9e838a143a12fdf119ecd01919936a437b5a2 (diff)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157976 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86Schedule.td')
-rw-r--r--lib/Target/X86/X86Schedule.td5
1 files changed, 1 insertions, 4 deletions
diff --git a/lib/Target/X86/X86Schedule.td b/lib/Target/X86/X86Schedule.td
index dc311b1..f670f28 100644
--- a/lib/Target/X86/X86Schedule.td
+++ b/lib/Target/X86/X86Schedule.td
@@ -8,7 +8,7 @@
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
-// Instruction Itinerary classes used for X86
+// Instruction Itinerary classes used for X86
def IIC_DEFAULT : InstrItinClass;
def IIC_ALU_MEM : InstrItinClass;
def IIC_ALU_NONMEM : InstrItinClass;
@@ -459,6 +459,3 @@ def IIC_NOP : InstrItinClass;
def GenericItineraries : ProcessorItineraries<[], [], []>;
include "X86ScheduleAtom.td"
-
-
-