llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.

This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 26 insertions, 26 deletions

diff --git a/lib/Target/XCore/XCoreAsmPrinter.cpp b/lib/Target/XCore/XCoreAsmPrinter.cpp
index 5234a9b..5874294 100644
--- a/lib/Target/XCore/XCoreAsmPrinter.cpp
+++ b/lib/Target/XCore/XCoreAsmPrinter.cpp
@@ -204,13 +204,13 @@ emitGlobal(const GlobalVariable *GV)
     case GlobalValue::PrivateLinkage:
       break;
     case GlobalValue::GhostLinkage:
-      LLVM_UNREACHABLE("Should not have any unmaterialized functions!");
+      llvm_unreachable("Should not have any unmaterialized functions!");
     case GlobalValue::DLLImportLinkage:
-      LLVM_UNREACHABLE("DLLImport linkage is not supported by this target!");
+      llvm_unreachable("DLLImport linkage is not supported by this target!");
     case GlobalValue::DLLExportLinkage:
-      LLVM_UNREACHABLE("DLLExport linkage is not supported by this target!");
+      llvm_unreachable("DLLExport linkage is not supported by this target!");
     default:
-      LLVM_UNREACHABLE("Unknown linkage type!");
+      llvm_unreachable("Unknown linkage type!");
     }
 
     EmitAlignment(Align, GV, 2);
@@ -255,7 +255,7 @@ emitFunctionStart(MachineFunction &MF)
   O << "\t.cc_top " << CurrentFnName << ".function," << CurrentFnName << "\n";
 
   switch (F->getLinkage()) {
-  default: LLVM_UNREACHABLE("Unknown linkage type!");
+  default: llvm_unreachable("Unknown linkage type!");
   case Function::InternalLinkage:  // Symbols default to internal.
   case Function::PrivateLinkage:
     break;
@@ -358,7 +358,7 @@ void XCoreAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
     if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
       O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
     else
-      LLVM_UNREACHABLE("not implemented");
+      llvm_unreachable("not implemented");
     break;
   case MachineOperand::MO_Immediate:
     O << MO.getImm();
@@ -381,7 +381,7 @@ void XCoreAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
       << '_' << MO.getIndex();
     break;
   default:
-    LLVM_UNREACHABLE("not implemented");
+    llvm_unreachable("not implemented");
   }
 }
 
@@ -410,7 +410,7 @@ void XCoreAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
   if (printInstruction(MI)) {
     return;
   }
-  LLVM_UNREACHABLE("Unhandled instruction in asm writer!");
+  llvm_unreachable("Unhandled instruction in asm writer!");
 }
 
 bool XCoreAsmPrinter::doInitialization(Module &M) {
diff --git a/lib/Target/XCore/XCoreISelLowering.cpp b/lib/Target/XCore/XCoreISelLowering.cpp
index c2cc09c..f6a181e 100644
--- a/lib/Target/XCore/XCoreISelLowering.cpp
+++ b/lib/Target/XCore/XCoreISelLowering.cpp
@@ -167,7 +167,7 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) {
   case ISD::SUB:              return ExpandADDSUB(Op.getNode(), DAG);
   case ISD::FRAMEADDR:        return LowerFRAMEADDR(Op, DAG);
   default:
-    LLVM_UNREACHABLE("unimplemented operand");
+    llvm_unreachable("unimplemented operand");
     return SDValue();
   }
 }
@@ -179,7 +179,7 @@ void XCoreTargetLowering::ReplaceNodeResults(SDNode *N,
                                              SelectionDAG &DAG) {
   switch (N->getOpcode()) {
   default:
-    LLVM_UNREACHABLE("Don't know how to custom expand this!");
+    llvm_unreachable("Don't know how to custom expand this!");
     return;
   case ISD::ADD:
   case ISD::SUB:
@@ -266,7 +266,7 @@ LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
       GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal());
   }
   if (! GVar) {
-    LLVM_UNREACHABLE("Thread local object not a GlobalVariable?");
+    llvm_unreachable("Thread local object not a GlobalVariable?");
     return SDValue();
   }
   const Type *Ty = cast<PointerType>(GV->getType())->getElementType();
@@ -275,7 +275,7 @@ LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
     cerr << "Size of thread local object " << GVar->getName()
         << " is unknown\n";
 #endif
-    llvm_unreachable();
+    llvm_unreachable(0);
   }
   SDValue base = getGlobalAddressWrapper(GA, GV, DAG);
   const TargetData *TD = TM.getTargetData();
@@ -292,7 +292,7 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG)
   // FIXME there isn't really debug info here
   DebugLoc dl = CP->getDebugLoc();
   if (Subtarget.isXS1A()) {
-    LLVM_UNREACHABLE("Lowering of constant pool unimplemented");
+    llvm_unreachable("Lowering of constant pool unimplemented");
     return SDValue();
   } else {
     MVT PtrVT = Op.getValueType();
@@ -356,7 +356,7 @@ ExpandADDSUB(SDNode *N, SelectionDAG &DAG)
 SDValue XCoreTargetLowering::
 LowerVAARG(SDValue Op, SelectionDAG &DAG)
 {
-  LLVM_UNREACHABLE("unimplemented");
+  llvm_unreachable("unimplemented");
   // FIX Arguments passed by reference need a extra dereference.
   SDNode *Node = Op.getNode();
   DebugLoc dl = Node->getDebugLoc();
@@ -426,7 +426,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG)
   switch (CallingConv) 
   {
     default:
-      LLVM_UNREACHABLE("Unsupported calling convention");
+      llvm_unreachable("Unsupported calling convention");
     case CallingConv::Fast:
     case CallingConv::C:
       return LowerCCCCallTo(Op, DAG, CallingConv);
@@ -474,7 +474,7 @@ LowerCCCCallTo(SDValue Op, SelectionDAG &DAG, unsigned CC)
 
     // Promote the value if needed.
     switch (VA.getLocInfo()) {
-      default: LLVM_UNREACHABLE("Unknown loc info!");
+      default: llvm_unreachable("Unknown loc info!");
       case CCValAssign::Full: break;
       case CCValAssign::SExt:
         Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
@@ -607,7 +607,7 @@ LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG)
   switch(CC) 
   {
     default:
-      LLVM_UNREACHABLE("Unsupported calling convention");
+      llvm_unreachable("Unsupported calling convention");
     case CallingConv::C:
     case CallingConv::Fast:
       return LowerCCCArguments(Op, DAG);
@@ -655,7 +655,7 @@ LowerCCCArguments(SDValue Op, SelectionDAG &DAG)
           cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
                << RegVT.getSimpleVT() << "\n";
 #endif
-          llvm_unreachable();
+          llvm_unreachable(0);
         }
       case MVT::i32:
         unsigned VReg = RegInfo.createVirtualRegister(
diff --git a/lib/Target/XCore/XCoreInstrInfo.cpp b/lib/Target/XCore/XCoreInstrInfo.cpp
index ea35504..ad47ac2 100644
--- a/lib/Target/XCore/XCoreInstrInfo.cpp
+++ b/lib/Target/XCore/XCoreInstrInfo.cpp
@@ -187,7 +187,7 @@ static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc)
 static inline unsigned GetCondBranchFromCond(XCore::CondCode CC) 
 {
   switch (CC) {
-  default: LLVM_UNREACHABLE("Illegal condition code!");
+  default: llvm_unreachable("Illegal condition code!");
   case XCore::COND_TRUE   : return XCore::BRFT_lru6;
   case XCore::COND_FALSE  : return XCore::BRFF_lru6;
   }
@@ -198,7 +198,7 @@ static inline unsigned GetCondBranchFromCond(XCore::CondCode CC)
 static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC)
 {
   switch (CC) {
-  default: LLVM_UNREACHABLE("Illegal condition code!");
+  default: llvm_unreachable("Illegal condition code!");
   case XCore::COND_TRUE   : return XCore::COND_FALSE;
   case XCore::COND_FALSE  : return XCore::COND_TRUE;
   }
@@ -408,7 +408,7 @@ void XCoreInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
                             const TargetRegisterClass *RC,
                             SmallVectorImpl<MachineInstr*> &NewMIs) const
 {
-  LLVM_UNREACHABLE("unimplemented");
+  llvm_unreachable("unimplemented");
 }
 
 void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
@@ -428,7 +428,7 @@ void XCoreInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
                               const TargetRegisterClass *RC,
                               SmallVectorImpl<MachineInstr*> &NewMIs) const
 {
-  LLVM_UNREACHABLE("unimplemented");
+  llvm_unreachable("unimplemented");
 }
 
 bool XCoreInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
diff --git a/lib/Target/XCore/XCoreRegisterInfo.cpp b/lib/Target/XCore/XCoreRegisterInfo.cpp
index 7773064..8bdfcdc 100644
--- a/lib/Target/XCore/XCoreRegisterInfo.cpp
+++ b/lib/Target/XCore/XCoreRegisterInfo.cpp
@@ -148,7 +148,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
         cerr << "eliminateCallFramePseudoInstr size too big: "
              << Amount << "\n";
 #endif
-        llvm_unreachable();
+        llvm_unreachable(0);
       }
 
       MachineInstr *New;
@@ -257,7 +257,7 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
               .addReg(ScratchReg, RegState::Kill);
         break;
       default:
-        LLVM_UNREACHABLE("Unexpected Opcode");
+        llvm_unreachable("Unexpected Opcode");
       }
     } else {
       switch (MI.getOpcode()) {
@@ -278,7 +278,7 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
               .addImm(Offset);
         break;
       default:
-        LLVM_UNREACHABLE("Unexpected Opcode");
+        llvm_unreachable("Unexpected Opcode");
       }
     }
   } else {
@@ -309,7 +309,7 @@ void XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
             .addImm(Offset);
       break;
     default:
-      LLVM_UNREACHABLE("Unexpected Opcode");
+      llvm_unreachable("Unexpected Opcode");
     }
   }
   // Erase old instruction.