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author | Bob Wilson <bob.wilson@apple.com> | 2010-07-08 17:45:26 +0000 |
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committer | Bob Wilson <bob.wilson@apple.com> | 2010-07-08 17:45:26 +0000 |
commit | 1425c6a92747acd904dfbb9c537e444e15b1ebdf (patch) | |
tree | 5788bd73efa1cf0c0a5bc4b237beb0eb3ccd5b7f /lib/Target | |
parent | 8190173350f4e4d916d2307278955b133fba8a00 (diff) | |
download | external_llvm-1425c6a92747acd904dfbb9c537e444e15b1ebdf.zip external_llvm-1425c6a92747acd904dfbb9c537e444e15b1ebdf.tar.gz external_llvm-1425c6a92747acd904dfbb9c537e444e15b1ebdf.tar.bz2 |
The NEONPreAllocPass should never have to assign fixed registers anymore.
This pass can go away entirely soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107892 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r-- | lib/Target/ARM/NEONPreAllocPass.cpp | 35 |
1 files changed, 1 insertions, 34 deletions
diff --git a/lib/Target/ARM/NEONPreAllocPass.cpp b/lib/Target/ARM/NEONPreAllocPass.cpp index e33a504..f67717c 100644 --- a/lib/Target/ARM/NEONPreAllocPass.cpp +++ b/lib/Target/ARM/NEONPreAllocPass.cpp @@ -468,40 +468,7 @@ bool NEONPreAllocPass::PreAllocNEONRegisters(MachineBasicBlock &MBB) { continue; if (FormsRegSequence(MI, FirstOpnd, NumRegs, Offset, Stride)) continue; - - MachineBasicBlock::iterator NextI = llvm::next(MBBI); - for (unsigned R = 0; R < NumRegs; ++R) { - MachineOperand &MO = MI->getOperand(FirstOpnd + R); - assert(MO.isReg() && MO.getSubReg() == 0 && "unexpected operand"); - unsigned VirtReg = MO.getReg(); - assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && - "expected a virtual register"); - - // For now, just assign a fixed set of adjacent registers. - // This leaves plenty of room for future improvements. - static const unsigned NEONDRegs[] = { - ARM::D0, ARM::D1, ARM::D2, ARM::D3, - ARM::D4, ARM::D5, ARM::D6, ARM::D7 - }; - MO.setReg(NEONDRegs[Offset + R * Stride]); - - if (MO.isUse()) { - // Insert a copy from VirtReg. - TII->copyRegToReg(MBB, MBBI, MO.getReg(), VirtReg, - ARM::DPRRegisterClass, ARM::DPRRegisterClass, - DebugLoc()); - if (MO.isKill()) { - MachineInstr *CopyMI = prior(MBBI); - CopyMI->findRegisterUseOperand(VirtReg)->setIsKill(); - } - MO.setIsKill(); - } else if (MO.isDef() && !MO.isDead()) { - // Add a copy to VirtReg. - TII->copyRegToReg(MBB, NextI, VirtReg, MO.getReg(), - ARM::DPRRegisterClass, ARM::DPRRegisterClass, - DebugLoc()); - } - } + llvm_unreachable("expected a REG_SEQUENCE"); } return Modified; |