changes to make it compatible with 64bit gcc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2791 91177308-0d34-0410-b5e6-96231b3b80d8

7 files changed, 12 insertions, 8 deletions

diff --git a/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp b/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp
index b27f902..c43f8dd 100644
--- a/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp
+++ b/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp
@@ -27,6 +27,7 @@
 #include "Support/CommandLine.h"
 #include <iostream>
 using std::cerr;
+using std::vector;
 
 //******************** Internal Data Declarations ************************/
 
@@ -152,7 +153,7 @@ SelectInstructionsForMethod(Function *F, TargetMachine &target)
 //-------------------------------------------------------------------------
 
 void
-InsertPhiElimInstructions(BasicBlock *BB, const vector<MachineInstr*>& CpVec)
+InsertPhiElimInstructions(BasicBlock *BB, const std::vector<MachineInstr*>& CpVec)
 { 
   Instruction *TermInst = (Instruction*)BB->getTerminator();
   MachineCodeForInstruction &MC4Term =MachineCodeForInstruction::get(TermInst);
@@ -294,7 +295,7 @@ SelectInstructionsForTree(InstrTreeNode* treeRoot, int goalnt,
   // 
   if (treeRoot->opLabel != VRegListOp)
     {
-      vector<MachineInstr*> minstrVec;
+      std::vector<MachineInstr*> minstrVec;
       
       InstructionNode* instrNode = (InstructionNode*)treeRoot;
       assert(instrNode->getNodeType() == InstrTreeNode::NTInstructionNode);
diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
index c7c9756..e884463 100644
--- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
@@ -28,6 +28,7 @@
 #include <iostream>
 #include <math.h>
 using std::cerr;
+using std::vector;
 
 RegAllocDebugLevel_t DEBUG_RA;
 static cl::Enum<RegAllocDebugLevel_t> DEBUG_RA_c(DEBUG_RA, "dregalloc",
diff --git a/lib/Target/SparcV9/SparcV9InstrInfo.cpp b/lib/Target/SparcV9/SparcV9InstrInfo.cpp
index 5fbced0..7bd8dd2 100644
--- a/lib/Target/SparcV9/SparcV9InstrInfo.cpp
+++ b/lib/Target/SparcV9/SparcV9InstrInfo.cpp
@@ -22,7 +22,7 @@
 #include "llvm/Instruction.h"
 #include "llvm/Constants.h"
 #include "llvm/DerivedTypes.h"
-
+using std::vector;
 
 //************************ Internal Functions ******************************/
 
diff --git a/lib/Target/SparcV9/SparcV9Internals.h b/lib/Target/SparcV9/SparcV9Internals.h
index b85b58f..b1a7ec3 100644
--- a/lib/Target/SparcV9/SparcV9Internals.h
+++ b/lib/Target/SparcV9/SparcV9Internals.h
@@ -455,16 +455,16 @@ public:
   // for an architecture.
   //
   void cpReg2RegMI(unsigned SrcReg, unsigned DestReg,
-                   int RegType, vector<MachineInstr*>& mvec) const;
+                   int RegType, std::vector<MachineInstr*>& mvec) const;
   
   void cpReg2MemMI(unsigned SrcReg, unsigned DestPtrReg,
-                   int Offset, int RegType, vector<MachineInstr*>& mvec) const;
+                   int Offset, int RegType, std::vector<MachineInstr*>& mvec) const;
 
   void cpMem2RegMI(unsigned SrcPtrReg, int Offset, unsigned DestReg,
-                   int RegType, vector<MachineInstr*>& mvec) const;
+                   int RegType, std::vector<MachineInstr*>& mvec) const;
 
   void cpValue2Value(Value *Src, Value *Dest,
-                     vector<MachineInstr*>& mvec) const;
+                     std::vector<MachineInstr*>& mvec) const;
 
   // To see whether a register is a volatile (i.e., whehter it must be
   // preserved acorss calls)
diff --git a/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp b/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
index 7243149..79f6871 100644
--- a/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
+++ b/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
@@ -52,7 +52,7 @@ namespace {
 
 void InsertPrologEpilogCode::InsertPrologCode(Function &F)
 {
-  vector<MachineInstr*> mvec;
+  std::vector<MachineInstr*> mvec;
   MachineInstr* M;
   const MachineFrameInfo& frameInfo = Target.getFrameInfo();
   
diff --git a/lib/Target/SparcV9/SparcV9RegClassInfo.cpp b/lib/Target/SparcV9/SparcV9RegClassInfo.cpp
index da40826..08e3324 100644
--- a/lib/Target/SparcV9/SparcV9RegClassInfo.cpp
+++ b/lib/Target/SparcV9/SparcV9RegClassInfo.cpp
@@ -4,6 +4,7 @@
 #include "llvm/Type.h"
 #include <iostream>
 using std::cerr;
+using std::vector;
 
 //-----------------------------------------------------------------------------
 // Int Register Class - method for coloring a node in the interference graph.
diff --git a/lib/Target/SparcV9/SparcV9RegInfo.cpp b/lib/Target/SparcV9/SparcV9RegInfo.cpp
index 6aa4d81..96ff5ad 100644
--- a/lib/Target/SparcV9/SparcV9RegInfo.cpp
+++ b/lib/Target/SparcV9/SparcV9RegInfo.cpp
@@ -22,6 +22,7 @@
 #include <iostream>
 #include <values.h>
 using std::cerr;
+using std::vector;
 
 UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt)
   : MachineRegInfo(tgt), UltraSparcInfo(&tgt), NumOfIntArgRegs(6),