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| author | Nate Begeman <natebegeman@mac.com> | 2008-02-10 18:47:57 +0000 |
|---|---|---|
| committer | Nate Begeman <natebegeman@mac.com> | 2008-02-10 18:47:57 +0000 |
| commit | ab5d56c6b974b5bcfa0b63e7ae024a53f0edd771 (patch) | |
| tree | c384bbaa1b41fcae1104f54f64d7fc9ae52bb406 /lib | |
| parent | 6f0d024a534af18d9e60b3ea757376cd8a3a980e (diff) | |
| download | external_llvm-ab5d56c6b974b5bcfa0b63e7ae024a53f0edd771.zip external_llvm-ab5d56c6b974b5bcfa0b63e7ae024a53f0edd771.tar.gz external_llvm-ab5d56c6b974b5bcfa0b63e7ae024a53f0edd771.tar.bz2 | |
xmm0 variable blends
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46931 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 29 |
1 files changed, 27 insertions, 2 deletions
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 3d70985..83e446c 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -3223,7 +3223,7 @@ let isTwoAddress = 1 in { def rri : SS4AI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3), !strconcat(OpcodeStr, - "\t{$$src3, src2, $dst|$dst, $src2, $src3}"), + "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>, OpSize { @@ -3232,7 +3232,7 @@ let isTwoAddress = 1 in { def rmi : SS4AI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3), !strconcat(OpcodeStr, - "\t{$$src3, src2, $dst|$dst, $src2, $src3}"), + "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), [(set VR128:$dst, (IntId128 VR128:$src1, (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>, @@ -3254,6 +3254,31 @@ defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw, 0>; +/// SS41I_binop_rmi_int - SSE 4.1 binary operator with immediate +let isTwoAddress = 1 in { + multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> { + def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1, VR128:$src2), + !strconcat(OpcodeStr, + "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"), + [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>, + OpSize; + + def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst), + (ins VR128:$src1, i128mem:$src2), + !strconcat(OpcodeStr, + "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"), + [(set VR128:$dst, + (IntId VR128:$src1, + (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize; + } +} + +defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>; +defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>; +defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>; + + multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> { def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), |