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author | Chris Lattner <sabre@nondot.org> | 2010-11-16 00:55:51 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2010-11-16 00:55:51 +0000 |
commit | b69cdfa6f3d5a0661354e744a11caa7b3342b83e (patch) | |
tree | 9aa1e2e5b83cb6c5bbb8c26c1dd931df914e4bb7 /lib | |
parent | b55e91e08738b804f17109a49881e51b69e91299 (diff) | |
download | external_llvm-b69cdfa6f3d5a0661354e744a11caa7b3342b83e.zip external_llvm-b69cdfa6f3d5a0661354e744a11caa7b3342b83e.tar.gz external_llvm-b69cdfa6f3d5a0661354e744a11caa7b3342b83e.tar.bz2 |
relax an assertion a bit, allowing the GPR argument of
these instructions to be encoded with getMachineOpValue.
This unbreaks ExecutionEngine/2003-01-04-ArgumentBug.ll
when running on a G5
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119307 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/PowerPC/PPCCodeEmitter.cpp | 5 | ||||
-rw-r--r-- | lib/Target/PowerPC/PPCMCCodeEmitter.cpp | 3 |
2 files changed, 6 insertions, 2 deletions
diff --git a/lib/Target/PowerPC/PPCCodeEmitter.cpp b/lib/Target/PowerPC/PPCCodeEmitter.cpp index 7c5fa7d..42232a0 100644 --- a/lib/Target/PowerPC/PPCCodeEmitter.cpp +++ b/lib/Target/PowerPC/PPCCodeEmitter.cpp @@ -246,7 +246,10 @@ unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI, const MachineOperand &MO) const { if (MO.isReg()) { - assert(MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF); + // MTCRF/MFOCRF should go through get_crbitm_encoding for the CR operand. + // The GPR operand should come through here though. + assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) || + MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7); return PPCRegisterInfo::getRegisterNumbering(MO.getReg()); } diff --git a/lib/Target/PowerPC/PPCMCCodeEmitter.cpp b/lib/Target/PowerPC/PPCMCCodeEmitter.cpp index ea5275a..b4a1b19 100644 --- a/lib/Target/PowerPC/PPCMCCodeEmitter.cpp +++ b/lib/Target/PowerPC/PPCMCCodeEmitter.cpp @@ -199,7 +199,8 @@ unsigned PPCMCCodeEmitter:: getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups) const { if (MO.isReg()) { - assert(MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF); + assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) || + MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7); return PPCRegisterInfo::getRegisterNumbering(MO.getReg()); } |