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| author | Stephen Hines <srhines@google.com> | 2014-06-03 18:31:47 -0700 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2014-06-03 18:31:47 -0700 |
| commit | 7b17ef61ee92cbea0cc4d321e95046d3179e21ad (patch) | |
| tree | 988ab12ef652cc1eaa1bd78f29cea111f7301338 /llvm-tblgen-rules.mk | |
| parent | 51c66e01e1137e01bbeff643f99f26264e96122e (diff) | |
| download | external_llvm-7b17ef61ee92cbea0cc4d321e95046d3179e21ad.zip external_llvm-7b17ef61ee92cbea0cc4d321e95046d3179e21ad.tar.gz external_llvm-7b17ef61ee92cbea0cc4d321e95046d3179e21ad.tar.bz2 | |
Switch name from tblgen -> llvm-tblgen for consistency with upstream LLVM.
Change-Id: I7735fd88104ff95001dd5f88a1c387df9af993ad
Diffstat (limited to 'llvm-tblgen-rules.mk')
| -rw-r--r-- | llvm-tblgen-rules.mk | 50 |
1 files changed, 25 insertions, 25 deletions
diff --git a/llvm-tblgen-rules.mk b/llvm-tblgen-rules.mk index 0746e8b..57be1a7 100644 --- a/llvm-tblgen-rules.mk +++ b/llvm-tblgen-rules.mk @@ -41,51 +41,51 @@ tblgen_td_deps := $(wildcard $(tblgen_td_deps)) ifeq ($(tblgen_source_dir),$(LLVM_ROOT_PATH)/lib/Target/ARM/MCTargetDesc) $(generated_sources)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(generated_sources)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td \ - $(tblgen_td_deps) | $(TBLGEN) + $(tblgen_td_deps) | $(LLVM_TBLGEN) $(call transform-td-to-out, register-info) $(generated_sources)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(generated_sources)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td \ - $(tblgen_td_deps) | $(TBLGEN) + $(tblgen_td_deps) | $(LLVM_TBLGEN) $(call transform-td-to-out,instr-info) $(generated_sources)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(generated_sources)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td \ - $(tblgen_td_deps) | $(TBLGEN) + $(tblgen_td_deps) | $(LLVM_TBLGEN) $(call transform-td-to-out,subtarget) endif ifeq ($(tblgen_source_dir),$(LLVM_ROOT_PATH)/lib/Target/X86/MCTargetDesc) $(generated_sources)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(generated_sources)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td \ - $(tblgen_td_deps) | $(TBLGEN) + $(tblgen_td_deps) | $(LLVM_TBLGEN) $(call transform-td-to-out, register-info) $(generated_sources)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(generated_sources)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td \ - $(tblgen_td_deps) | $(TBLGEN) + $(tblgen_td_deps) | $(LLVM_TBLGEN) $(call transform-td-to-out,instr-info) $(generated_sources)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(generated_sources)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td \ - $(tblgen_td_deps) | $(TBLGEN) + $(tblgen_td_deps) | $(LLVM_TBLGEN) $(call transform-td-to-out,subtarget) endif ifeq ($(tblgen_source_dir),$(LLVM_ROOT_PATH)/lib/Target/Mips/MCTargetDesc) $(generated_sources)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(generated_sources)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td \ - $(tblgen_td_deps) | $(TBLGEN) + $(tblgen_td_deps) | $(LLVM_TBLGEN) $(call transform-td-to-out, register-info) $(generated_sources)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(generated_sources)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td \ - $(tblgen_td_deps) | $(TBLGEN) + $(tblgen_td_deps) | $(LLVM_TBLGEN) $(call transform-td-to-out,instr-info) $(generated_sources)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(generated_sources)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td \ - $(tblgen_td_deps) | $(TBLGEN) + $(tblgen_td_deps) | $(LLVM_TBLGEN) $(call transform-td-to-out,subtarget) endif @@ -93,112 +93,112 @@ endif ifneq ($(filter %GenRegisterInfo.inc,$(tblgen_gen_tables)),) $(generated_sources)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(generated_sources)/%GenRegisterInfo.inc: $(tblgen_source_dir)/%.td \ - $(tblgen_td_deps) | $(TBLGEN) + $(tblgen_td_deps) | $(LLVM_TBLGEN) $(call transform-td-to-out,register-info) endif ifneq ($(filter %GenInstrInfo.inc,$(tblgen_gen_tables)),) $(generated_sources)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(generated_sources)/%GenInstrInfo.inc: $(tblgen_source_dir)/%.td \ - $(tblgen_td_deps) | $(TBLGEN) + $(tblgen_td_deps) | $(LLVM_TBLGEN) $(call transform-td-to-out,instr-info) endif ifneq ($(filter %GenAsmWriter.inc,$(tblgen_gen_tables)),) $(generated_sources)/%GenAsmWriter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(generated_sources)/%GenAsmWriter.inc: $(tblgen_source_dir)/%.td \ - $(tblgen_td_deps) | $(TBLGEN) + $(tblgen_td_deps) | $(LLVM_TBLGEN) $(call transform-td-to-out,asm-writer) endif ifneq ($(filter %GenAsmWriter1.inc,$(tblgen_gen_tables)),) $(generated_sources)/%GenAsmWriter1.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(generated_sources)/%GenAsmWriter1.inc: $(tblgen_source_dir)/%.td \ - $(tblgen_td_deps) | $(TBLGEN) + $(tblgen_td_deps) | $(LLVM_TBLGEN) $(call transform-td-to-out,asm-writer -asmwriternum=1) endif ifneq ($(filter %GenAsmMatcher.inc,$(tblgen_gen_tables)),) $(generated_sources)/%GenAsmMatcher.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(generated_sources)/%GenAsmMatcher.inc: $(tblgen_source_dir)/%.td \ - $(tblgen_td_deps) | $(TBLGEN) + $(tblgen_td_deps) | $(LLVM_TBLGEN) $(call transform-td-to-out,asm-matcher) endif ifneq ($(filter %GenCodeEmitter.inc,$(tblgen_gen_tables)),) $(generated_sources)/%GenCodeEmitter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(generated_sources)/%GenCodeEmitter.inc: $(tblgen_source_dir)/%.td \ - $(tblgen_td_deps) | $(TBLGEN) + $(tblgen_td_deps) | $(LLVM_TBLGEN) $(call transform-td-to-out,emitter) endif ifneq ($(filter %GenMCCodeEmitter.inc,$(tblgen_gen_tables)),) $(generated_sources)/%GenMCCodeEmitter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(generated_sources)/%GenMCCodeEmitter.inc: $(tblgen_source_dir)/%.td \ - $(tblgen_td_deps) | $(TBLGEN) + $(tblgen_td_deps) | $(LLVM_TBLGEN) $(call transform-td-to-out,emitter -mc-emitter) endif ifneq ($(filter %GenMCPseudoLowering.inc,$(tblgen_gen_tables)),) $(generated_sources)/%GenMCPseudoLowering.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(generated_sources)/%GenMCPseudoLowering.inc: $(tblgen_source_dir)/%.td \ - $(tblgen_td_deps) | $(TBLGEN) + $(tblgen_td_deps) | $(LLVM_TBLGEN) $(call transform-td-to-out,pseudo-lowering) endif ifneq ($(filter %GenDAGISel.inc,$(tblgen_gen_tables)),) $(generated_sources)/%GenDAGISel.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(generated_sources)/%GenDAGISel.inc: $(tblgen_source_dir)/%.td \ - $(tblgen_td_deps) | $(TBLGEN) + $(tblgen_td_deps) | $(LLVM_TBLGEN) $(call transform-td-to-out,dag-isel) endif ifneq ($(filter %GenDisassemblerTables.inc,$(tblgen_gen_tables)),) $(generated_sources)/%GenDisassemblerTables.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(generated_sources)/%GenDisassemblerTables.inc: $(tblgen_source_dir)/%.td \ - $(tblgen_td_deps) | $(TBLGEN) + $(tblgen_td_deps) | $(LLVM_TBLGEN) $(call transform-td-to-out,disassembler) endif ifneq ($(filter %GenEDInfo.inc,$(tblgen_gen_tables)),) $(generated_sources)/%GenEDInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(generated_sources)/%GenEDInfo.inc: $(tblgen_source_dir)/%.td \ - $(tblgen_td_deps) | $(TBLGEN) + $(tblgen_td_deps) | $(LLVM_TBLGEN) $(call transform-td-to-out,enhanced-disassembly-info) endif ifneq ($(filter %GenFastISel.inc,$(tblgen_gen_tables)),) $(generated_sources)/%GenFastISel.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(generated_sources)/%GenFastISel.inc: $(tblgen_source_dir)/%.td \ - $(tblgen_td_deps) | $(TBLGEN) + $(tblgen_td_deps) | $(LLVM_TBLGEN) $(call transform-td-to-out,fast-isel) endif ifneq ($(filter %GenSubtargetInfo.inc,$(tblgen_gen_tables)),) $(generated_sources)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(generated_sources)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/%.td \ - $(tblgen_td_deps) | $(TBLGEN) + $(tblgen_td_deps) | $(LLVM_TBLGEN) $(call transform-td-to-out,subtarget) endif ifneq ($(filter %GenCallingConv.inc,$(tblgen_gen_tables)),) $(generated_sources)/%GenCallingConv.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(generated_sources)/%GenCallingConv.inc: $(tblgen_source_dir)/%.td \ - $(tblgen_td_deps) | $(TBLGEN) + $(tblgen_td_deps) | $(LLVM_TBLGEN) $(call transform-td-to-out,callingconv) endif ifneq ($(filter %GenIntrinsics.inc,$(tblgen_gen_tables)),) $(generated_sources)/%GenIntrinsics.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(generated_sources)/%GenIntrinsics.inc: $(tblgen_source_dir)/%.td \ - $(tblgen_td_deps) | $(TBLGEN) + $(tblgen_td_deps) | $(LLVM_TBLGEN) $(call transform-td-to-out,tgt_intrinsics) endif ifneq ($(findstring ARMGenDecoderTables.inc,$(tblgen_gen_tables)),) $(generated_sources)/ARMGenDecoderTables.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(generated_sources)/ARMGenDecoderTables.inc: $(tblgen_source_dir)/ARM.td \ - $(tblgen_td_deps) | $(TBLGEN) + $(tblgen_td_deps) | $(LLVM_TBLGEN) $(call transform-td-to-out,arm-decoder) endif |