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author | Pirama Arumuga Nainar <pirama@google.com> | 2015-04-10 22:08:18 +0000 |
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committer | Android Git Automerger <android-git-automerger@android.com> | 2015-04-10 22:08:18 +0000 |
commit | 13a7db5b9c4f5e543d037be68ec3428216bfd550 (patch) | |
tree | 1b2c9792582e12f5af0b1512e3094425f0dc0df9 /test/CodeGen/AArch64/logical_shifted_reg.ll | |
parent | 0eb46f5d1e06a4284663d636a74b06adc3a161d7 (diff) | |
parent | 31195f0bdca6ee2a5e72d07edf13e1d81206d949 (diff) | |
download | external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.zip external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.gz external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.bz2 |
am 31195f0b: Merge "Update aosp/master llvm for rebase to r233350"
* commit '31195f0bdca6ee2a5e72d07edf13e1d81206d949':
Update aosp/master llvm for rebase to r233350
Diffstat (limited to 'test/CodeGen/AArch64/logical_shifted_reg.ll')
-rw-r--r-- | test/CodeGen/AArch64/logical_shifted_reg.ll | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/test/CodeGen/AArch64/logical_shifted_reg.ll b/test/CodeGen/AArch64/logical_shifted_reg.ll index b249d72..6b3246d 100644 --- a/test/CodeGen/AArch64/logical_shifted_reg.ll +++ b/test/CodeGen/AArch64/logical_shifted_reg.ll @@ -8,8 +8,8 @@ define void @logical_32bit() minsize { ; CHECK-LABEL: logical_32bit: - %val1 = load i32* @var1_32 - %val2 = load i32* @var2_32 + %val1 = load i32, i32* @var1_32 + %val2 = load i32, i32* @var2_32 ; First check basic and/bic/or/orn/eor/eon patterns with no shift %neg_val2 = xor i32 -1, %val2 @@ -98,8 +98,8 @@ define void @logical_32bit() minsize { define void @logical_64bit() minsize { ; CHECK-LABEL: logical_64bit: - %val1 = load i64* @var1_64 - %val2 = load i64* @var2_64 + %val1 = load i64, i64* @var1_64 + %val2 = load i64, i64* @var2_64 ; First check basic and/bic/or/orn/eor/eon patterns with no shift %neg_val2 = xor i64 -1, %val2 @@ -191,8 +191,8 @@ define void @logical_64bit() minsize { define void @flag_setting() { ; CHECK-LABEL: flag_setting: - %val1 = load i64* @var1_64 - %val2 = load i64* @var2_64 + %val1 = load i64, i64* @var1_64 + %val2 = load i64, i64* @var2_64 ; CHECK: tst {{x[0-9]+}}, {{x[0-9]+}} ; CHECK: b.gt .L |