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-rw-r--r--test/CodeGen/AArch64/logical_shifted_reg.ll12
1 files changed, 6 insertions, 6 deletions
diff --git a/test/CodeGen/AArch64/logical_shifted_reg.ll b/test/CodeGen/AArch64/logical_shifted_reg.ll
index b249d72..6b3246d 100644
--- a/test/CodeGen/AArch64/logical_shifted_reg.ll
+++ b/test/CodeGen/AArch64/logical_shifted_reg.ll
@@ -8,8 +8,8 @@
define void @logical_32bit() minsize {
; CHECK-LABEL: logical_32bit:
- %val1 = load i32* @var1_32
- %val2 = load i32* @var2_32
+ %val1 = load i32, i32* @var1_32
+ %val2 = load i32, i32* @var2_32
; First check basic and/bic/or/orn/eor/eon patterns with no shift
%neg_val2 = xor i32 -1, %val2
@@ -98,8 +98,8 @@ define void @logical_32bit() minsize {
define void @logical_64bit() minsize {
; CHECK-LABEL: logical_64bit:
- %val1 = load i64* @var1_64
- %val2 = load i64* @var2_64
+ %val1 = load i64, i64* @var1_64
+ %val2 = load i64, i64* @var2_64
; First check basic and/bic/or/orn/eor/eon patterns with no shift
%neg_val2 = xor i64 -1, %val2
@@ -191,8 +191,8 @@ define void @logical_64bit() minsize {
define void @flag_setting() {
; CHECK-LABEL: flag_setting:
- %val1 = load i64* @var1_64
- %val2 = load i64* @var2_64
+ %val1 = load i64, i64* @var1_64
+ %val2 = load i64, i64* @var2_64
; CHECK: tst {{x[0-9]+}}, {{x[0-9]+}}
; CHECK: b.gt .L