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authorDan Gohman <gohman@apple.com>2009-01-13 20:24:13 +0000
committerDan Gohman <gohman@apple.com>2009-01-13 20:24:13 +0000
commitbc0b56732a2d1dc22767e0f3930f22a76d99470a (patch)
treeca0c8659323b4d12946471be758a50bbd2d96735 /test/CodeGen/Mips
parent6893cd76152e805291c3c9f36fa81b330846434d (diff)
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The list-td and list-tdrr schedulers don't yet support physreg
scheduling dependencies. Add assertion checks to help catch this. It appears the Mips target defaults to list-td, and it has a regression test that uses a physreg dependence. Such code was liable to be miscompiled, and now evokes an assertion failure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62177 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Mips')
-rw-r--r--test/CodeGen/Mips/2008-07-23-fpcmp.ll1
1 files changed, 1 insertions, 0 deletions
diff --git a/test/CodeGen/Mips/2008-07-23-fpcmp.ll b/test/CodeGen/Mips/2008-07-23-fpcmp.ll
index 7bc1f42..ebb9c8a 100644
--- a/test/CodeGen/Mips/2008-07-23-fpcmp.ll
+++ b/test/CodeGen/Mips/2008-07-23-fpcmp.ll
@@ -1,6 +1,7 @@
; RUN: llvm-as < %s | llc -march=mips -f -o %t
; RUN: grep {c\\..*\\.s} %t | count 3
; RUN: grep {bc1\[tf\]} %t | count 3
+; XFAIL: *
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "mipsallegrexel-psp-elf"