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authorStephen Lin <stephenwlin@gmail.com>2013-07-13 20:38:47 +0000
committerStephen Lin <stephenwlin@gmail.com>2013-07-13 20:38:47 +0000
commitb4dc0233c9f70e8cf946822811f233bb613a02e9 (patch)
tree6cb47482e15d250ae95e5c6c96abd2afb56f6fca /test/CodeGen/PowerPC/vec_constants.ll
parentae4e1a94e3fb7d1d2d0eec6eb7d04b74326c8453 (diff)
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Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion.
This was done with the following sed invocation to catch label lines demarking function boundaries: sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186258 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/vec_constants.ll')
-rw-r--r--test/CodeGen/PowerPC/vec_constants.ll16
1 files changed, 8 insertions, 8 deletions
diff --git a/test/CodeGen/PowerPC/vec_constants.ll b/test/CodeGen/PowerPC/vec_constants.ll
index e4799e5..f16b9f5 100644
--- a/test/CodeGen/PowerPC/vec_constants.ll
+++ b/test/CodeGen/PowerPC/vec_constants.ll
@@ -17,14 +17,14 @@ define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) nounwind {
store <4 x float> %tmp13, <4 x float>* %P3
ret void
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK-NOT: CPI
}
define <4 x i32> @test_30() nounwind {
ret <4 x i32> < i32 30, i32 30, i32 30, i32 30 >
-; CHECK: test_30:
+; CHECK-LABEL: test_30:
; CHECK: vspltisw
; CHECK-NEXT: vadduwm
; CHECK-NEXT: blr
@@ -33,7 +33,7 @@ define <4 x i32> @test_30() nounwind {
define <4 x i32> @test_29() nounwind {
ret <4 x i32> < i32 29, i32 29, i32 29, i32 29 >
-; CHECK: test_29:
+; CHECK-LABEL: test_29:
; CHECK: vspltisw
; CHECK-NEXT: vspltisw
; CHECK-NEXT: vsubuwm
@@ -43,7 +43,7 @@ define <4 x i32> @test_29() nounwind {
define <8 x i16> @test_n30() nounwind {
ret <8 x i16> < i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30 >
-; CHECK: test_n30:
+; CHECK-LABEL: test_n30:
; CHECK: vspltish
; CHECK-NEXT: vadduhm
; CHECK-NEXT: blr
@@ -52,7 +52,7 @@ define <8 x i16> @test_n30() nounwind {
define <16 x i8> @test_n104() nounwind {
ret <16 x i8> < i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104 >
-; CHECK: test_n104:
+; CHECK-LABEL: test_n104:
; CHECK: vspltisb
; CHECK-NEXT: vslb
; CHECK-NEXT: blr
@@ -61,7 +61,7 @@ define <16 x i8> @test_n104() nounwind {
define <4 x i32> @test_vsldoi() nounwind {
ret <4 x i32> < i32 512, i32 512, i32 512, i32 512 >
-; CHECK: test_vsldoi:
+; CHECK-LABEL: test_vsldoi:
; CHECK: vspltisw
; CHECK-NEXT: vsldoi
; CHECK-NEXT: blr
@@ -70,7 +70,7 @@ define <4 x i32> @test_vsldoi() nounwind {
define <8 x i16> @test_vsldoi_65023() nounwind {
ret <8 x i16> < i16 65023, i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023 >
-; CHECK: test_vsldoi_65023:
+; CHECK-LABEL: test_vsldoi_65023:
; CHECK: vspltish
; CHECK-NEXT: vsldoi
; CHECK-NEXT: blr
@@ -79,7 +79,7 @@ define <8 x i16> @test_vsldoi_65023() nounwind {
define <4 x i32> @test_rol() nounwind {
ret <4 x i32> < i32 -11534337, i32 -11534337, i32 -11534337, i32 -11534337 >
-; CHECK: test_rol:
+; CHECK-LABEL: test_rol:
; CHECK: vspltisw
; CHECK-NEXT: vrlw
; CHECK-NEXT: blr