diff options
| author | Hal Finkel <hfinkel@anl.gov> | 2013-09-12 05:24:49 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-09-12 05:24:49 +0000 |
| commit | 411dea0e7206ccc8018261831225d898d069ff1d (patch) | |
| tree | 986de438669a3155018bbb0f19c7339cb43eb956 /test/CodeGen/PowerPC | |
| parent | 9ec1a55a863f658292b19d7a3c167ba089134dff (diff) | |
| download | external_llvm-411dea0e7206ccc8018261831225d898d069ff1d.zip external_llvm-411dea0e7206ccc8018261831225d898d069ff1d.tar.gz external_llvm-411dea0e7206ccc8018261831225d898d069ff1d.tar.bz2 | |
PPC: Enable aggressive anti-dependency breaking
Aggressive anti-dependency breaking is enabled by default for all PPC cores.
This provides a general speedup on the P7 and other platforms (among other
factors, the instruction group formation for the non-embedded PPC cores is done
during post-RA scheduling). In order to do this safely, the incompatibility
between uses of the MFOCRF instruction and anti-dependency breaking are
resolved by marking MFOCRF with hasExtraSrcRegAllocReq. As noted in the removed
FIXME, the problem was that MFOCRF's output is sensitive to the identify of the
source register, and always paired with a shift to undo this effect. Because
anti-dependency breaking is unaware of this hidden dependency of the shift
amount on the source register of the MFOCRF instruction, changing that register
must be inhibited.
Two test cases were adjusted: The SjLj test was made more insensitive to
register choices and scheduling; the saveCR test disabled anti-dependency
breaking because part of what it is testing is proper register reuse.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190587 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC')
| -rw-r--r-- | test/CodeGen/PowerPC/2010-02-12-saveCR.ll | 2 | ||||
| -rw-r--r-- | test/CodeGen/PowerPC/sjlj.ll | 27 |
2 files changed, 15 insertions, 14 deletions
diff --git a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll index 097611a..b0c37b8 100644 --- a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll +++ b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=powerpc-apple-darwin -mcpu=g4 | FileCheck %s +; RUN: llc < %s -mtriple=powerpc-apple-darwin -mcpu=g4 -break-anti-dependencies=none | FileCheck %s ; ModuleID = 'hh.c' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32" target triple = "powerpc-apple-darwin9.6" diff --git a/test/CodeGen/PowerPC/sjlj.ll b/test/CodeGen/PowerPC/sjlj.ll index 410109d..414640b 100644 --- a/test/CodeGen/PowerPC/sjlj.ll +++ b/test/CodeGen/PowerPC/sjlj.ll @@ -64,15 +64,16 @@ return: ; preds = %if.end, %if.then ; CHECK: std ; Make sure that we're not saving VRSAVE on non-Darwin: ; CHECK-NOT: mfspr -; CHECK: stfd -; CHECK: stvx -; CHECK: addis [[REG:[0-9]+]], 2, env_sigill@toc@ha -; CHECK: std 31, env_sigill@toc@l([[REG]]) -; CHECK: addi [[REG]], [[REG]], env_sigill@toc@l -; CHECK: std [[REG]], [[OFF:[0-9]+]](31) # 8-byte Folded Spill -; CHECK: std 1, 16([[REG]]) -; CHECK: std 2, 24([[REG]]) +; CHECK-DAG: stfd +; CHECK-DAG: stvx + +; CHECK-DAG: addis [[REG:[0-9]+]], 2, env_sigill@toc@ha +; CHECK-DAG: std 31, env_sigill@toc@l([[REG]]) +; CHECK-DAG: addi [[REGA:[0-9]+]], [[REG]], env_sigill@toc@l +; CHECK-DAG: std [[REGA]], [[OFF:[0-9]+]](31) # 8-byte Folded Spill +; CHECK-DAG: std 1, 16([[REGA]]) +; CHECK-DAG: std 2, 24([[REGA]]) ; CHECK: bcl 20, 31, .LBB1_1 ; CHECK: li 3, 1 ; CHECK: #EH_SjLj_Setup .LBB1_1 @@ -134,11 +135,11 @@ return: ; preds = %if.end, %if.then ; CHECK: addis [[REG:[0-9]+]], 2, env_sigill@toc@ha ; CHECK: std 31, env_sigill@toc@l([[REG]]) -; CHECK: addi [[REG]], [[REG]], env_sigill@toc@l -; CHECK: std [[REG]], [[OFF:[0-9]+]](31) # 8-byte Folded Spill -; CHECK: std 1, 16([[REG]]) -; CHECK: std 2, 24([[REG]]) -; CHECK: std 30, 32([[REG]]) +; CHECK: addi [[REGB:[0-9]+]], [[REG]], env_sigill@toc@l +; CHECK-DAG: std [[REGB]], [[OFF:[0-9]+]](31) # 8-byte Folded Spill +; CHECK-DAG: std 1, 16([[REGB]]) +; CHECK-DAG: std 2, 24([[REGB]]) +; CHECK-DAG: std 30, 32([[REGB]]) ; CHECK: bcl 20, 31, ; CHECK: blr |